Patrice Quinton

The ALPHA language and its use for the design of systolic arrays

The ALPHA language results from research on automatic synthesis of systolic algorithms. It is based on the recurrence equation formalism introduced by Karp, Miller and Winograd in 1967. The basic objects of ALPHA are variables indexed on integral points of a convex set. It is a functional/equational language, whose definition is particularly well-suited to express regular algorithms, as well as transformations of these algorithms from their initial mathematical specification to an implementation on a synchronous parallel architecture. In particular, ALPHA makes it easy to define, prove and implement basic transformations such as Leiserson and Saxes retiming, space-time reindexing, localization, and partitioning.We describe ALPHA, its use for expressing and deriving systolic arrays, and the design environment ALPHA DU CENTAUR for this language.

Computability of recurrence equations

Abstract Systems of uniform recurrence equations were proposed by Karp et al. (1967) as a means to derive automatically programs for parallel architectures. Since then, extensions of this formalism were used by many authors, in particular, in the fields of systolic array synthesis. The computability of a system of recurrence equations is, therefore, of primary importance, and is considered as the first point to be examined when trying to implement an algorithm. This paper investigates the computability of recurrence equations. We first recall the results established by Karp et al. (1967) on the computability of systems of uniform recurrence equations, by Rao (1985) on regular iterative arrays, and Joinnaults (1987) undecidability result on the computability of conditional systems of uniform recurrence equations with nonbounded domain. Then we consider systems of parameterized affine recurrence equations, that is to say, systems of recurrence equations whose domains depend linearly on a size parameter, and establish that the computability of such system is also undecidable.

Systolic Gaussian elimination over GF(p) with partial pivoting

A systolic architecture is proposed for the triangularization by means of the Gaussian elimination algorithm of large dense n*n matrices over GF(p), where p is a prime number. The solution of large dense linear systems over GF(p) is the major computational step in various algorithms issuing from arithmetic number theory and computer algebra. The proposed architecture implements the elimination with partial pivoting, although the operation of the array remains purely systolic. Extension of the array to the complete solution of a linear system Ax=b over GF(p) is also considered. >

ompVerify: polyhedral analysis for the OpenMP programmer

We describe a static analysis tool for OpenMP programs integrated into the standard open source Eclipse IDE. It can detect an important class of common data-race errors in OpenMP parallel loop programs by flagging incorrectly specified omp parallel for directives and data races. The analysis is based on the polyhedral model, and covers a class of program fragments called Affine Control Loops (ACLs, or alternatively, Static Control Parts, SCoPs). ompVerify automatically extracts such ACLs from an input C program, and then flags the errors as specific and precise error messages reported to the user. We illustrate the power of our techniques through a number of simple but non-trivial examples with subtle parallelization errors that are difficult to detect, even for expert OpenMP programmers.

Hardware synthesis for multi-dimensional time

We introduce some basic principles for extending the classical systolic synthesis methodology to multidimensional time. Multidimensional scheduling enables complex algorithms that do not admit linear schedules to be parallelized, but it also requires the use of memories in the architecture. We explain how to obtain compatible allocation and memory functions for VLSI (or SIMD-like code) generation. We also present an original mechanism for controlling a VLSI architecture that has a multidimensional schedule. A structural VHDL code has been derived and synthesized (for implementation on FPGA platforms) using these systematic design principles. These results are preliminary steps to the hardware synthesis for multidimensional time.

Acceleration of a content-based image-retrieval application on the RDISK cluster

Because of the growing use of multimedia content over Internet, content-based image retrieval (CBIR) has recently received a lot of interest. While accurate search techniques based on local image descriptors exist, they suffer from very long execution time. We propose to accelerate CBIR on the RDISK machine, a cluster of FPGA-enhanced hard-drives, that follows the philosophy of smart-disks. Our platform combines coarse and fine grain parallelism thanks to the concurrent use of the cluster nodes and of a programmable logic device. The implementation of the CBIR application on this mixed hardware/software platform follows a strict methodology, that was validated on realistic data-set (image database of more than 30,000 images). This methodology allows us to adapt the original algorithm to suit a hardware implementation, and to select the values of some key design parameters to maximize global performance. Our preliminary results indicate that speed-ups between 120 and 200 could be obtained for a cluster of 32 nodes compared with a software implementation running on a standard desktop PC

Derivation of systolic algorithms for the algebraic path problem by recurrence transformations

Abstract In this paper, we are interested in solving the algebraic path problem (APP) on regular arrays. We first unify previous contributions with recurrence transformations. Then, we propose a new localization technique without long-range communication which leads to a piecewise affine scheduling of 4 n + Θ (1) steps, where n is the size of the problem. The derivation of a locally connected space-time minimal solution with respect to the new scheduling constitutes the second contribution of the paper. This new design requires n 2 /3+ Θ ( n ) elementary processors and solves the problem in 4 n + Θ (1) steps, and this includes loading and unloading time. This is an improvement over the best previously known bounds.

Synthesis of a new systolic architecture for the algebraic path problem

Abstract This paper deals with the systematic synthesis of systolic arrays. As a target example, we design a new 2D toroidal systolic array for the algebraic path problem. First, we informally explain how to derive this new systolic architecture, then we show how to synthesize it using a systematic methodology based upon uniform recurrence equations. Such a synthesis provides a proof of the correctness of the architecture.

Efficient nested loop pipelining in high level synthesis using polyhedral bubble insertion

Loop pipelining is a key transformation in high-level synthesis tools as it helps maximizing both computational throughput and hardware utilization. Nevertheless, it somewhat looses its efficiency when dealing with small trip-count inner loops, as the pipeline latency overhead quickly limits its efficiency. Even if it is possible to overcome this limitation by pipelining the execution of a whole loop nest, the applicability of nested loop pipelining has so far been limited to a very narrow subset of loops, namely perfectly nested loops with constant bounds. In this work we propose to extend the applicability of nested-loop pipelining to imperfectly nested loops with affine dependencies by leveraging on the so-called polyhedral model. We show how such loop nest can be analyzed, and under certain conditions, how one can modify the source code in order to allow nested loop pipeline to be applied using a method called polyhedral bubble insertion. We also discuss the implementation of our method in a source-to-source compiler specifically targeted at High-Level Synthesis tools.

On Manipulating Z-Polyhedra Using a Canonical Representation

Z-polyhedra are intersections of polyhedra and integral lattices. They arise in the domain of automatic parallelization and VLSI array synthesis. In this paper, we address the problem of computation on Z-polyhedra. We introduce a canonical representation for Z-polyhedra which allows one to perform comparisons and transformations of Z-polyhedra with the help of a computational kernel on polyhedra.