Steven Derrien

Systolic array for computing the pixel purity index algorithm on hyperspectral images

The Pixel Purity Index (PPI) algorithm is used as a pre-processing to find end-members in a hyper spectral image. It tries to identify pure spectra by assigning a pixel purity index to each pixel in the image. The algorithm proceeds by generating a large number of random vectors through the hyper spectral image and by computing a dot-product between each vector and all the pixels. Since the number of random vectors is high (a few thousands), this algorithm may require hours of computation on standard computers. We present a systolic implementation of the PPI algorithm. It is based on a linear systolic array connected to a host processor through its external I/O bus system. In this scheme, the image is stored on the host processor memory and flushed several times through the array. The performance is mainly dictated by the I/O bus bandwidth and the ability to implement large systolic arrays: the fewer the passes needed through the array, the better the performance. The hardware implementation targets Xilinx Virtex boards, but the specification is independent of the platform: no external memories are required and the architecture works whatever the size of the linear systolic array. Experiments carried out on a low-cost reconfigurable board (a single Xilinx Virtex 800) show a speed-up of two orders of magnitude compared to a software implementation.

Communication-Based Power Modelling for Heterogeneous Multiprocessor Architectures

Programming heterogeneous multiprocessor architectures is a real challenge dealing with a huge design space. Computer-aided design and development tools try to circumvent this issue by simplifying instantiation mechanisms. However, energy consumption is not well supported in most of these tools due to the difficulty to obtain fast and accurate power estimation. To this aim, this paper proposes and validates a power model for such platforms. The methodology is based on micro-benchmarking to estimate the model parameters. The energy model mainly relies on the energy overheads induced by communications between processors in a parallel application. Power modelling and micro-benchmarks are validated using a Zynq-based heterogeneous architecture showing the accuracy of the model for several tested synthetic applications.