Patrick M. Williams

IBM POWER6 microprocessor physical design and design methodology

The IBM POWER6™ microprocessor is a 790 million-transistor chip that runs at a clock frequency of greater than 4 GHz. The complexity and size of the POWER6 microprocessor, together with its high operating frequency, present a number of significant challenges. This paper describes the physical design and design methodology of the POWER6 processor. Emphasis is placed on aspects of the design methodology, technology, clock distribution, integration, chip analysis, power and performance, random logic macro (RLM), and design data management processes that enabled the design to be completed and the project goals to be met.

Deep submicron design techniques for the 500 MHz IBM S/390 G5 custom microprocessor

High frequency microprocessor designs require rigorous design guidelines, design methodology advancements, and novel approaches in circuit design style for processors operating in the high megahertz range. Timing closure becomes the single most important design issue, however other design metrics such as area, power and noise need to be given equal consideration within the design cycle. Custom design techniques were used through out the logic circuits and arrays as well as the overall design planning for the 500 MHz microprocessor cycle time.

Design methods for attaining IBM System z9 processor cycle-time goals

Cycle-time targets were set for the IBM System z9TM processor subsystem prior to building the system, and achieving these targets was one of the biggest challenges we faced during hardware development. In particular, although the processor-subsystem cycle-time improvement was driven primarily by the technology migration from CMOS 9S (130-nm lithography) for the prior IBM System z990 to CMOS IOSO (90-nm lithography) for the new system, the cooling capability for the System z9 resulted from a direct migration of the System z990 implementation with very limited improvements. The higher device current leakage and power associated with the technology migration, combined with the fixed cooling capability, created a technology challenge in which the subsystem cycle time and performance were potentially limited by cooling capability. Our solution emphasized silicon technology development, chip design, and hardware characterization and tuning. Ultimately, the System z9 processor subsystem achieved operation at 1.7 GHz, which exceeded the original target.

Analysis and results of net coupling within a high performance microprocessor

A methodology based on closed form expressions is applied to predict noise and timing impact due U) line to line coupling. Statistical results for a S/3W microprocessor is shown for over 20,000 nets. The trends in CMOS chip design have all been converging to women coupling between horizontally and verticalIy adjacent wires. The coupling between on chip wires can cause two different types of problems, namely, functional fails due to the induced coupled noise voltage, and changes in delay due to the changes in load capacitance caused by switch- ing the activity of adjacent wires. On-chip net topologies have unique electrical characteristics(l) which differ greatly fiom packaging structures such as PCB and MCMs. Fine line wire geometries have significant series resistance which tend to negate induerive effects well into the multi-GHZ range. Under such conditions, on-chip signal wires can be characterized ptimarily as either a lumped a distributed RC network depending on the accuracy required for timing considerations. The extraction of these electrical parameters for the entire chip assuming a 2D cross-section is a well developed discipline in the chip design community. This paper will present a methodology for calculating both the noise voltage magnitude and the increase in delay for alI the global nets on a high performance microprocessor chip. Recent developments in the area of global 3D capacitance exaaction(2) not only account for the environnmental effects on the total capacitance but associate a coupling capacitance for each adjacent signal line in close proximity to the net of interest. Therefore the total capacitance for each net is the sum of the reference capacitance plus all coupling capac- itances. With this information available, a link to associate a noise voltage from each active net unto a quiet or target net can be established. The prediction of acceptable noise levels on a net by net basis requires a compilation of timing and patametic param- eters which are readily available from various chip design databases. Such information as line and driver resistance as well as 3D cap extract is used to predict the noise magnitude of each active element on the line, while timing windows predict noise arrival times and susceptability intervals on the quiet net. A similar process has been applied to first and sec- ond level packages(3) and extended to on-chip nets without regards to stochastic considerations. This process is illustrated in Figure 1, where two active nets couple at various positions along the quiet net. Current limitations in 3D enviromental extraction do not provide the position location of the coupling segments. Therefore, each coupling segment is assumed to be located at the quiet receiver and driven directly by the active nets sources. To calcu- late the total noise, a linear sum of each individual noise voltage is computed, based on superposition, and it is assumed that all active nets switch at the Same time. The peak noise voltage can be computed based on the following parameters as shown in equation (1) where Cji is the coupling capacitance between the quiet net and the active net, Trad is the transition time of the active driver, Rqline is the quiet nets line resistance, Rqd is the quiet nets driver resistance in the linear operation of the FET transistor, and finally the Cself is the total self capacitance of the quiet net. Using these parameters a closed loop equation can be derived as closely approximating the peak far end voltage noise that is present at a receiver. VSpkT = f(Cji, Trad, Rqline, Rqd, Cself) (1) The basic equation for predicting the noise is given in (4). In considering long lines and minimum width wire this equation is optimistic since quiet net iine resistance is not included which limits the quiet nets driver in holding the line during a quiescent state. In addition, as mentioned before, the quiet nets driver resistance should actually be computed in the linear operation of the FET transistor (at Vds=O, Vgs=Vdd) since the quiet nets driver has already switched and oper- ation of the driver is in this range during the injection of coupled noise. Referring to Figure 2, simulations were performed breaking a quiet nets segment where a portion of the segment was a distributed coupling RC line model dong modelling the coupling between the nets with the other portion was a distrib- uted RC line model. (All capacitances tied to ground). Also, during the simulations, actual FETS configured as inverters were used for quiet nets driver and active nets driver. It was found that the equation in (21 under predicted the noise since the line resistance was not included. In addition, it was also found that equation (2) also falls short in predicting the noise since the coupling capacitance and the self capacitance is distributed along the quiet net.