Theodore W. Houston

An SEU resistant 256 K SOI SRAM

A novel SEU (single event upset) resistant SRAM (static random access memory) cell has been implemented in a 256 K SOI (silicon on insulator) SRAM that has attractive performance characteristics over the military temperature range of -55 to +125 degrees C. These include worst-case access time of 40 ns with an active power of only 150 mW at 25 MHz, and a worst-case minimum WRITE pulse width of 20 ns. Measured SEU performance gives an Adams 10% worst-case error rate of 3.4*10/sup -11/ errors/bit-day using the CRUP code with a conservative first-upset LET threshold. Modeling does show that higher bipolar gain than that measured on a sample from the SRAM lot would produce a lower error rate. Measurements show the worst-case supply voltage for SEU to be 5.5 V. Analysis has shown this to be primarily caused by the drain voltage dependence of the beta of the SOI parasitic bipolar transistor. Based on this, SEU experiments with SOI devices should include measurements as a function of supply voltage, rather than the traditional 4.5 V, to determine the worst-case condition. >

A shallow trench isolation study for 0.25/0.18 /spl mu/m CMOS technologies and beyond

A manufacturable shallow trench isolation (STI) technology using high density plasma (HDP) CVD oxide as trench filling material is reported for the first time, and compared to using sub-atmospheric CVD (SACVD) oxide as filling material. HDP filled STI has excellent immunity to double-hump, better gate oxide integrity and inverse narrow width effect, due to its lower deglaze rate and thus better corner protection compared to the SACVD case. The /spl Delta/Vt (between W=10 and 0.18 /spl mu/m) are 150 mV (NMOS). And 60 mV (PMOS) for the HDP case, and the transistor width reduction is /spl les/0.03 /spl mu/m for both cases. Trench wall passivation and a low sputtering component during deposition are necessary for HDP to achieve low diode edge leakage. 0.28 /spl mu/m intra-well isolation (or 0.46 /spl mu/m min. pitch), 0.6 /spl mu/m n/sup +/-to-p/sup +/ isolation, latch-up holding voltage of 2 V at 0.5 /spl mu/m n/sup +/-to-p/sup +/ spacing, together with outstanding CMOS transistor and inverter performance, have been achieved. These results are either comparable to or better than the best results reported to date. It is concluded that HDP trench filling oxide is a viable approach, while SACVD oxide is marginally acceptable, for the STI of 0.25/0.18 /spl mu/m CMOS.

Characterization of bit transistors in a functional SRAM

A direct bit transistor access (DBTA) scheme is proposed and implemented in 8 Mb SRAMpsilas at 65 nm and 45 nm nodes. It allows, for the first time, characterization of each bit transistor in a functional SRAM. It thus enables (a) collection of transistor data across bit arrays, (b) collection of massive data for statistical analysis such as on transistor mismatch and NBTI Vt drift, and (c) collection of data for fast failure analysis. Measured data are presented.

A 65 nm CMOS technology for mobile and digital signal processing applications

This paper presents a 65 nm CMOS technology that achieves a logic density of 900 k-gates/mm/sup 2/ and a SRAM memory density of 1.4 Mb/mm/sup 2/ using a sub-0.49 /spl mu/m/sup 2/ bitcell. Key features of a low cost technology option for mobile products (MP) and a high performance technology option (HP) for DSP based applications are described.

A guide to simulation of hysteretic gate delays based on physical understanding [SOI logic]

Studies of floating body effects in SOI transistors and circuits have been widely reported. Nevertheless, in part because of the complexities of the device physics and the inaccuracies of numerical simulations, there is still need for a physical understanding of the floating body effect to guide a circuit designer in evaluation of the resulting hysteretic gate delay. This paper describes the dynamics of the floating-body effect in terms familiar to the circuit designer (voltages, capacitive coupling, and diode currents) and proposes a methodology for specification of body voltages for bounding circuit delay. This methodology is developed for inverters and can be extended to complex gates. A basis for detecting inaccuracies in SPICE simulations is included. Data showing the effect of drain-to-body capacitance on hysteretic behaviour is presented.

Transistor optimization for leakage power management in a 65 nm CMOS technology for wireless and mobile applications

This paper presents a transistor optimization methodology tailored for wireless, digital consumer, and mobile applications that employ power management circuit techniques. This methodology is applied to a 65nm technology that supports a high-density (<0.5 um/sup 2/) embedded 6T SRAM cell. High performance logic (I/sub dn//I/sub dp/ = 550/300uA/um at L/sub poly/ = 39nm) and low leakage are achieved simultaneously by employing a data retention mode for the SRAM (I/sub leakage/ /spl sim/2pA/bit). Retention mode bias conditions and selective gate sizing in the SRAM reduces leakage by /spl sim/300X. Advanced transistor design including SSR channel, strain engineering, drain-extension (HDD) offset spacer, and HDD and halo profile optimization is used to achieve at least an additional 4/spl times/ reduction in leakage.

Fabrication and performance of submicron silicon MESFET

Micron and submicron gate length silicon MESFET devices and circuits have been successfully fabricated using electron beam direct slice writing and a newly developed high density structure which self-aligns the active channel, source-drain, and contacts to the field oxide. Device characteristics of 1/4, 3/4, and 1 micron gate lengths show good square law behavior. In addition, measurements of 15-stage enhancement logic ring oscillators with 1 micron gate lengths show switching speeds of 1 to 2 nanoseconds with speed-power products of 1 to 5 femto Joules.

A novel dynamic Vt circuit configuration

Summary form only given. It is a well known dilemma that as supply voltages are scaled lower, CMOS threshold voltages must also be scaled lower to maintain performance, leading to increased subthreshold leakage. One solution to mitigate the trade-off between high performance and low standby current is to modulate the threshold voltage by control of the well or body voltage, lowering the Vt in active mode and raising the Vt in standby. SOI is particularly suited for this because of the relatively low body capacitance, and the wider practical range of body vs well voltage. Developing circuit techniques to leverage this advantage may be critical to the successful commercialization of SOI technology. In this work, we propose a modification of the drain-to-body configuration that significantly reduces gate delay and is particularly appropriate for large drivers where a series of inverters is used. The basic configuration is to tie the drain of the transistor to the body of the transistor when the transistor is turned on, disconnecting it when the transistor is off. To evaluate the circuit design technique, simulations were run for a variety of configurations for three inverters in series.

A Screening Methodology for VMIN Drift in SRAM Arrays with Application to Sub-65nm Nodes

SRAMs are an integral part of system on chip devices. With transistor and gate length scaling to 65nm/45nm nodes, SRAM stability across the products lifetime has become a challenge. Negative bias temperature instability, defects, or other phenomena that may manifest itself as a transistor threshold voltage (VT) increase can result in VMIN drift of SRAM memory cells through burn-in and/or operation. A direct assessment at time-zero is difficult because the transistor VT has not yet shifted, and therefore no capability to screen VMIN shift at time zero can be developed. This work describes a methodology developed on 65nm low power and high performance process technologies at Texas Instruments for screening SRAM cells at time zero before they become reliability issues

Ultra-thin film SOI/CMOS with selective-epi source/drain for low series resistance, high drive current

A self-aligned selective epitaxial technique is used to overcome the high source/drain resistance problem in ultra-thin film SOI/CMOS devices. Very low series resistances, comparable to those for bulk CMOS devices, are demonstrated with this selective-epi source/drain.<<ETX>>