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Saul Barajas

Unisys

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Publication

Featured researches published by Saul Barajas.

Archive | 1996

Cache invalidation sequence system utilizing odd and even invalidation queues with shorter invalidation cycles

Saul Barajas; David M. Kalish; Bruce Ernest Whittaker; Keith Saldanha

Archive | 1993

Storage queue with adjustable level thresholds for cache invalidation systems in cache oriented computer architectures

Saul Barajas; David M. Kalish; Bruce Ernest Whittaker

Archive | 1993

Cache memory system with fault tolerance having concurrently operational cache controllers processing disjoint groups of memory

David M. Kalish; Saul Barajas; Paul B. Ricci

Archive | 1990

Multiprocessor multifunction arbitration system with two levels of bus access including priority and normal requests

Bruce Ernest Whittaker; Saul Barajas; Leland E. Watson

Archive | 1990

Clocked logic circuitry preventing double driving on shared data bus

Bruce Ernest Whittaker; Saul Barajas; Leland E. Watson

Archive | 1992

System for optional module detection and reconfiguration

Saul Barajas; Leland E. Watson; Bruce Ernest Whittaker

Archive | 1993

Programmable, multi-purpose virtual pin multiplier

David M. Kalish; Saul Barajas; Bruce Ernest Whittaker

Archive | 1992

Inter-processor communication net

Bruce Ernest Whittaker; Saul Barajas; Leland E. Watson

Archive | 1997

Apparatus and method for compressing a plurality of contiguous addresses to form a compressed block address using the first address of the contiguous addresses and a block identifier bit

Bruce Ernest Whittaker; Donald M. Kalish; Saul Barajas

Archive | 1990

Flexible gate array system for combinatorial logic

Bruce Ernest Whittaker; Saul Barajas

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Bruce Ernest Whittaker

Unisys

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David M. Kalish

Unisys

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Leland E. Watson

Unisys

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Donald M. Kalish

Unisys

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Paul B. Ricci

Unisys

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Keith Saldanha

Unisys

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