Paul Cheng-Po Liang

A Distributed Oscillator Based All-Digital PLL With a 32-Phase Embedded Phase-to-Digital Converter

This paper presents a wide-bandwidth, low-noise 4 GHz All-Digital PLL. It uses a rotary traveling wave oscillator (RTWO) as the oscillator core. By using multiphase signals available from the RTWO, the analog phase information is directly converted into the digital domain. Unlike the conventional time-to-digital converter (TDC) approach, it eliminates power hungry inverter delay chains as well as real time period normalization. The proposed approach significantly simplifies the ADPLL architecture while maintaining excellent phase noise. The PLL is implemented in a 65 nm CMOS process. The 32-phase embedded phase-to-digital converter (PDC) achieves 2π/64 phase resolution. The measured in-band phase noise is -108 dBc/Hz at 4 GHz with a 78 MHz reference and a 1 MHz loop bandwidth.

A rotary-traveling-wave-oscillator-based all-digital PLL with a 32-phase embedded phase-to-digital converter in 65nm CMOS

All-digital phase-locked loops (ADPLLs) have recently become more popular as possible alternatives to conventional analog charge-pump-based PLLs [1]. Currently, most of the ADPLLs are based on a time-to-digital converter (TDC) utilizing inverter delay chains. There have been tremendous efforts to improve TDC performance, i.e., maximizing resolution and reducing power consumption, but they normally require additional complex circuits.