Paul J. M. van Adrichem

Determining OPC target specifications electrically instead of geometrically

Deep sub-wavelength optical lithography significantly distorts the shape of transistor channel, particularly causing gate corner rounding at the beginning of active area (i.e. active margin), due to proximity effect. Optical Proximity Correction (OPC) aims at compensating for lithography induced geometry distortion, but still could not completely fix geometry distortion especially corner rounding. The OPC target specification of corner rounding at active margin, i.e. how many nanometer of corner rounding is allowed, is usually determined subjectively based geometric specs without considering the actual electrical performance impact on transistor. Instead of determining the OPC corner rounding target specs geometrically, we proposed a methodology to determine corner rounding specs electrically, particularly in this case, based on the impact on transistor drain current in saturation mode. We first assessed the impact of corner rounding on transistor drain current using a first order analytical model, then compared it with the HSPICE simulation result using a non-rectangular transistor channel whose shape was obtained through post-OPC lithography simulation. Reasonably good agreement was observed between the first order model approach and the HSPICE simulation based approach, which is more rigorous intrinsically. This methodology can also be used in the determination of lithography process specification such as misalignment between active and poly gate layers.

Novel apodization and pellicle optical models for accurate optical proximity correction modeling at 45 and 32 nm

An accurate optical model is the foundation of an accurate optical proximity correction (OPC) model, which has always been the key for successful implementation of model-based OPC. As critical dimension (CD) control requirements become severe at the 45- and 32-nm device generations, OPC model accuracy and hence optical model accuracy requirements become more stringent. In previous generations, certain optical effects could be safely ignored. For example, the transmission attenuation particularly at high spatial frequencies caused by lens apodization effects and organic pellicle films was ignored or not accurately modeled in conventional OPC simulators. These effects are now playing a more important role in OPC modeling as technology scales down. Our simulations indicate these effects can cause CD modeling errors of 5 nm or larger, at the 45-nm technology node and beyond. Therefore, they must be accurately modeled in OPC modeling. In our OPC modeling methodology, we propose two novel low-pass-filter models to capture the frequency-dependent transmission attenuation due to lens apodization and to pellicle films. These parameterized novel low-pass-filter models ensure that lens apodization and pellicle-film-induced transmission attenuation can be appropriately account for through regression during the experimental OPC model calibration stage in the case where no measured transmission data are available, thus enabling physics-centric OPC model building with considerably higher accuracy. We can then avoid overfitting the OPC model, which could cause instability in the OPC correction stage. The validity and efficiency of the proposed novel models are also verified using an industry-standard lithography simulator as well as an experimental OPC model calibration at the 45-nm technology node.

A practical alternating PSM modeling and OPC approach to deal with 3D mask effects for the 65nm node and beyond

Alternating PSM (Alt-PSM) has been recognized as a logical Resolution Enhancement Technique (RET) candidate for the 65nm technology node. One of the key properties this technique has to offer is high Depth of Focus (DOF) and lower Mask Error Enhancement Factor (MEEF). The so-called image imbalance is an Alt-PSM specific property which, if not dealt with correctly, constrains the added DOF. Because of mask topography, intensity differences caused by light scattering become evident between π (180°) and zero degree phase shifters. This causes a line shift that is inversely proportional to the pitch. The traditional solution of applying a fixed trench bias increases the width if the π phase shifter to level out intensities and thus minimize image imbalance. This technique may no longer be sufficient at the 65nm technology node. With the requirement to print even smaller pitches together with a tighter Critical Dimension (CD) budget, intensity imbalance is a larger concern. It may be necessary to apply a pitch dependent or variable trench bias. In this paper, we present a practical OPC modeling approach that accounts for image imbalance. The 2D modeling approach uses boundary layers to represent the 3D effect of light scattering. We demonstrate that with the boundary layer model, it is possible to predict image imbalance caused by mask 3D effects. The model can then be used either to determine the nominal trench bias or can be integrated into the OPC engine to apply a variable trench bias. Results are compared to rigorous Electro Magnetic Field (EMF) simulations and experimental exposures using an ArF scanner, targeting pitches of 130nm and above.

Application of layout DOE in RET flow

At low k1 lithography and strong off-axis illumination, it is very hard to achieve edge-placement tolerances and 2-D image fidelity requirements for some layout configurations. Quite often these layouts are within simple design rules constraint for a given technology node. Evidently it is important to have these layouts included during early RET flow development. Simple shrinkage from previous technology node is quite common, although often not enough. For logic designs, it is hard to control design styles. Moreover for engineers in fabless design groups, it is difficult to assess the manufacturability of their layouts because of the lack of understanding of the litho process. Assist features (AF) are frequently placed according to pre-determined rules to improve lithography process window. These rules are usually derived from lithographic models. Direct validation of AF rules is required at development phase.To ensure good printability through process window, process aware optical proximity correction (OPC) recipes were developed. Generally rules based correction is performed before model based correction. Furthermore, there are also lots of other options and parameters in OPC recipes for an advanced technology, thus making it difficult to holistically optimize performance of recipe bearing all these variables in mind. In this paper we demonstrate the application of layout DOE in RET flow development. Layout pattern libraries are generated using the Synopsys Test Pattern Generator (STPG), which is embedded in a layout tool (ICWB). Assessment gauges are generated together with patterns for quick correction accuracy assessment. OPC verification through full process is also deployed. Several groups of test pattern libraries for different applications are developed, ranging from simple 1D pattern for process capability study and settings of process aware parameters to a full set of patterns for the assessment of rules based correction, line end and corner interaction, active and poly interaction, and critical patterns for contact coverage, etc. Restrictive design rules (RDR) are commonly deployed to eliminate problematic layouts. We demonstrate RDR evaluation and validation using our layout design of experiments (DOE) approach. This technique of layout DOE also offers a simple and yet effective way to verify AF placement rules. For a given nominal layout features all possible assist features are generated within the mask rules constraint using STPG. Then we run OPC correction and assess main feature critical dimension (CD) at best and worst process condition in ICWB. Best assist feature placement rules are derived based on minimum CD difference. The rules derived from this approach are not the same as those derived from the commonly used method of least intensity variation.

Full-chip process window aware OPC capability assessment

In the past technology generations, Optical Proximity Correction (OPC) has been applied using a model capturing the Optical proximity effects in a single focal plane. In the newer generations, this method is more and more difficult to maintain because of very small process windows in specific situations. These specific situations include 1D configurations (e.g. isolated small lines) but increasingly complex 2D configurations. In the more advanced technology nodes 2D configuration are starting to play a much bigger role. Process windows need to be preserved in all cases, and so this brings about another challenge for the OPC flow. The more traditional OPC approaches may result in un-acceptable small process window in such cases, whereas well characterized Process Window aware OPC (PW-OPC) can provide better results, with much less engineering interventions. In this paper the method of Process Window aware OPC is applied on special designed test structures and on a larger scale (full chip). Verifications and assessments are demonstrated and compared with alternatives. In the past OPC engineers have been pushing for more and more design constraints in order to allow the OPC flow to be successful. The PW-OPC approach is more adaptive compared with traditional single focal plane OPC, and can still converge to an acceptable solution in complicated (unforeseen) layout configurations, without the need to introduce complicated design constraints.

OPC development in action for advanced technology nodes

In leading edge technologies, Optical Proximity Correction (OPC) plays a critical role in the total imaging flow. Large investments in terms of time and engineering resources are made to obtain the required models and recipes to get the OPC job done. In the model building area, the metrology component is becoming more and more critical. Questions like which structures to put in a calibration pattern, how to measure, where to measure them, and how often has a serious impact on the calibration dataset, and thus on the final model. Corner rounding starts to become an increasingly important factor in imaging and device performance. Because of this, the model 2D behavior needs to be verified as the least, using reliable metric. In this paper two techniques are described. Finally the cost of model building is discussed. When the number of measurements for a model calibration is considered, available machine time almost always plays a key role. In this paper, a slightly different approach is made on this problem by looking at the cost of the different components of model calibration, and how that is going to progress in the process generations to come.

Hyper-NA model validation for the 45-nm node

Over the years process development engineers found creative ways to extent the capabilities of existing imaging techniques to enable production of the next technology node. For the 45nm node the immersion technology is being prepared for production, along with other resolutions enhancement techniques such as illuminator polarization. In parallel with the development of these tools, modeling techniques are being developed, which are needed in order to establish the design flows and to set up the Optical Proximity Correction (OPC) and mask data preparation. There is a clear need to validate these models and verify them in an early stage. With the equipment not being available yet, other methods like Maxwell simulators and special test equipment are used for such validations. In this paper initial model verification and validation work is presented of a hyper NA models developed for the 45nm technology node. Models with different illuminator settings are used and compared with Maxwell simulators and experimental measurements obtained with an Exitech MS-193i immersion micro-exposure tool.

Reducing alternating phase shift mask (Alt-PSM) write-time through mask data optimization

Resolution enhancement techniques (RETs) such as optical proximity correction (OPC), phase-shifting masks (PSM), sub-resolution assist features (SRAF) have become essential components in the sub-90nm silicon manufacturing process. For the 65nm generation, alternating phase shift masks (Alt-PSM) is recognized as a proven wafer imaging technique. The large process window and hence stable process control is one of the key properties which make it the most viable approach for 65nm production compared with other RET approaches. On the mask making side, the good mask error enhancement factor (MEEF) performance of the Alt-PSM is a big plus as it makes the wafer CD control less susceptible for CD errors on the mask. Even though the benefits of Alt-PSM are well known, the reticle cost and manufacturing challenges have impeded its extensive adoption. In this work, we explore a methodology to reduce the Alt-PSM mask write time vis-a-vis cost, through certain data optimization techniques.

An efficient resolution enhancement technique flow for 65nm logic poly layer

For the manufacturing of 65nm technology devices, many exposure techniques that have been used in previous technology nodes cannot offer enough process window anymore. Alternating Aperture Phase Shift Mask (Alt-PSM) is one of the few remaining technologies that still offer enough resolution to enable 65nm production. While setting up a 65nm Alt-PSM based resolution enhancement technique (RET) flow many of the mask manufacturability challenges need to be considered and addressed. At the same time OPC complexity is one of the main factors for increased data volume and high mask costs. In this work, logic and embedded memory cells are designed, and based on the specific geometries a manufacturable RET flow is developed. Data complexity reduction and lower mask cost are the primary motives in setting up this RET flow.

65nm mask CD qualification on critical features through simulation based lithography verification

For leading edge technologies, mask critical dimension (CD) errors consume a substantial part of the total wafer CD budget. Moreover, the strong optical proximity effects (OPE) can make the impact of a CD error on the mask significantly worse on wafer. At the same time, the mask making capabilities as far as CD control can barely keep up with the wafer fab requirements. To assess the overall mask quality ever more mask CD measurements are taken in the mask qualification process. These measurement points are increasingly placed in the main die area and are often selected in a more or less random fashion. An improved assessment of the mask CD quality can be achieved by taking advantage of the lithography verification step. The wafer simulation capability in the Silicon versus Layout (SiVL) tool is used to identify the high mask error enhancement factor (MEEF), error prone locations on a critical layer. The mask CD qualification process can be improved by including these poor MEEF and error prone sites. In this work, an automated flow is presented in which mask qualification sites are selected based on simulated wafer image contrast.