Paul Leroux

Low-voltage low-power CMOS-RF transceiver design

Research over the last ten years has resulted in attempts toward single-chip CMOS RF circuits for Bluetooth, global positioning system, digital enhanced cordless telecommunications and cellular applications. An overview of the use of CMOS for low-cost integration of a high-end cellular RF transceiver front-end is presented. Some fundamental pitfalls and limitations of RF CMOS are discussed. To circumvent these obstacles, the choice of transceiver architecture, circuit topology design, and systematic optimization of the different transceiver blocks is necessary. Moreover, optimization of the transceiver as one single block by minimizing the number of power-hungry interface circuits is emphasized. As examples, a fully integrated cellular transceiver front-end, a low-power extremely low noise-figure low-noise amplifier, and a very efficient power amplifier are demonstrated.

A 0.8-dB NF ESD-Protected 9-mW CMOS LNA operating at 1.23 GHz [for GPS receiver]

The GPS L2 band, centered at 1.2276 GHz, is planned to enhance the capabilities of civil GPS to backup the conventional GPS L1 link. As the L2 receiver is required to detect a low power signal, an LNA with extremely low noise figure is required. In addition, the LNA must exhibit a large gain to suppress noise from the subsequent stages. This ESD-protected CMOS LNA meets these requirements.

A 63,000 Q-factor relaxation oscillator with switched-capacitor integrated error feedback

There is a growing interest in implementing on-chip reference clock generators for low-cost low-power area-efficient SoCs, such as implantable biomedical devices and microcomputers. Relaxation oscillators are suitable candidates to generate such reference clocks due to their compact size, low power consumption and wide frequency tuning range. However, the poor phase noise performance and large long-term variation are two major problems that limit their application.

A fully-integrated GPS receiver front-end with 40 mW power consumption

A 0.25 /spl mu/m CMOS quadrature complex bandpass low-IF GPS receiver includes an LNA, PLL, mixer and a continuous-time /spl Delta//spl Sigma/ ADC. The chip has -130 dBm input sensitivity, 62 dB DR, and -32 dB IMRR, while consuming 40 mW from 2 V supply. The chip is 9 mm/sup 2/.

LNA-ESD co-design for fully integrated CMOS wireless receivers

Abstract. List of Symbols and Abbreviations. 1 Introduction. 1.1 The Growth of the Wireless Communication Market. 1.2 Evolution to CMOS RF. 1.3 CMOS, RF and ESD. 1.4 Outline of this Book. 2 Low-Noise Amplifiers in CMOS Wireless Receivers. 2.1 Introduction. 2.2 Some Important RF Concepts. 2.2.1 Quality Factor of Reactive Elements and Series-Parallel Transformation. 2.2.2 SNR and Noise Figure. 2.2.3 Impedance Matching, Power Matching, Noise Matching. 2.2.4 Transducer Power Gain, Operating Power Gain and Available Power Gain. 2.2.5 Intermodulation Distortion. 2.3 The Deep Sub-Micron MOS Transistor at Radio Frequencies. 2.3.1 MOS Model for Hand Calculations. 2.3.2 Linearity of the short-channel MOS transistor. 2.3.3 Non-Quasi Static Model. 2.3.4 Extended MOS Model for Simulation. 2.4 The Origin of Noise. 2.4.1 Resistor Thermal Noise. 2.4.2 Thermal Noise in MOS transistors. 2.4.2.1 Classical MOS Channel Noise. 2.4.2.2 Induced Gate Noise. 2.4.3 1/f Noise. 2.4.4 Shot Noise. 2.5 The LNA in the Receiver Chain. 2.5.1 Cascading Non-Ideal Building Blocks. 2.5.1.1 Noise in a Cascade. 2.5.1.2 IIV3 of a Cascade. 2.5.2 Wireless Receiver Architectures. 2.5.3 LNA Requirements. 2.5.3.1 Matching. 2.5.3.2 Noise Figure. 2.5.3.3 Voltage Gain or Power Gain. 2.5.3.4 Intermodulation Distortion. 2.5.3.5 Reverse Isolation. 2.5.3.6 Stability. 2.5.3.7 Single-ended vs. Differential. 2.6 Topologies for Low-Noise Amplifiers. 2.6.1 The Inductively Degenerated Common Source LNA. 2.6.1.1 From Basic Common-Source Amplifier to Inductively Degenerated Common-Source LNA. 2.6.1.2 Power Gain. 2.6.1.3 Noise Figure. 2.6.1.4 Linearity. 2.6.2 The Common-Gate LNA. 2.6.2.1 Input Matching. 2.6.2.2 Power Gain. 2.6.2.3 Noise Figure. 2.6.2.4 Linearity. 2.6.3 Shunt-Feedback Amplifier. 2.6.4 Image Reject LNAs. 2.6.5 Highly Linear Feedforward LNA. 2.6.6 The Noise-Cancelling Wide-band LNA. 2.6.7 Current Reuse LNA with Interstage Resonance. 2.6.8 Transformer Feedback LNA. 2.7Conclusion. 3 ESD Protection in CMOS. 3.1 Introduction. 3.2 ESD Tests and Standards. 3.2.1 Human Body Model. 3.2.2 Machine Model. 3.2.3 Charged Device Model. 3.2.4 Transmission Line Pulsing. 3.3 ESD-Protection in CMOS. 3.3.1 ESD-Protection Devices. 3.3.1.1 Diode. 3.3.1.2 Grounded-Gate NMOS. 3.3.1.3 Gate-Coupled NMOS. 3.3.1.4 Silicon-Controlled Rectifier. 3.3.2 ESD-Protection Topologies. 3.3.2.1 I/O Pins. 3.3.2.2 Power Supply Clamping. 3.4 Conclusion. 4 Detailed Study of the Common-Source LNA with Inductive Degeneration. 4.1 Introduction. 4.2 The Non-Quasi Static Gate Resistance. 4.2.1 Influence of rg NQS on Zin, GT and IIP3. 4.2.2 Influence of rg NQS on the Noise Figure. 4.3 Parasitic Input Capacitance. 4.3.1 Impact of Cp. 4.3.1.1 Influence of Cp on Input Matching. 4.3.1.2 Influence of Cp on Power Gain, Noise Figure and IIP3. 4.3.2 Impact of Cp Non-Linearity. 4.3.3 Impact of the Finite Q of Cp. 4.4 Miller Capacitance. 4.5 Optimization of the Cascode Transistor. 4.6 Output Capacitance Non-Linearity. 4.7 Impact of a Non-Zero S11 . 4.8 Output Considerations. 4.8.1 Load Impedance Constraints. 4.8.2 Output Matching. 4.9 LNA Bandwidth. 4.10 Layout Aspects. 4.10.1 RF Bonding Pads. 4.10.2 On-Chip Inductors. 4.10.2.1 Modelling. 4.10.2.2 Patterned Ground Shields. 4.10.3 The Amplifying Transistor. 4.10.4 The Cascode Transistor. 4.11 The Common-Gate LNA Revisited. 4.12 Conclusion. 5 RF-ESD Co-Design for CMOS LNAs. 5.1 Introduction. 5.2 ESD-protection within an L-Type Matching Network. 5.2.1 Introduction. 5.2.2 General Performance. 5.2.3 Design and Layout of the ESD Protection Diodes. 5.2.4 Non-Linearity of Input ESD Protection Diodes. 5.2.5 Conclusion. 5.3 ESD-Protection within a _-Type Matching Network. 5.4 Inductive ESD-Protection. 5.5 Comparison. 5.6 Other ESD-Protection Strategies. 5.6.1 Distributed ESD-Protection. 5.6.2 ESD-Protection with T-Coils. 5.7 ESD-Protection for the Common-Gate LNA. 5.8 Conclusion. 6

A 0.8 dB NF ESD-protected 9 mW CMOS LNA

The GPS L2 band, centered at 1.2276 GHz, is planned to enhance the capabilities of civil GPS to backup the conventional GPS L1 link. As the L2 receiver is required to detect a low power signal, an LNA with extremely low noise figure is required. In addition, the LNA must exhibit a large gain to suppress noise from the subsequent stages. This ESD-protected CMOS LNA meets these requirements.

A 5 GHz CMOS low-noise amplifier with inductive ESD protection exceeding 3 kV HBM

This work presents a 5 GHz LNA with on-chip ESD-protection provided by an integrated inductor. The circuit is implemented in a standard 0.18 /spl mu/m CMOS technology. The LNA is matched at both input and output. It achieves a power gain of 20 dB with a noise figure of 3.5 dB at a power consumption of only 15 mW including the output buffer. The protection level complies with the class II HBM standard of 2 kV.

A 1.7mW 11b 1–1–1 MASH ΔΣ time-to-digital converter

Recently, high-resolution TDCs have gained more and more popularity due to their increasing implementation in digital PLLs, ADCs, jitter measurement and time-of-flight measurement units. Similar to ADCs, existing architectures of TDCs can be divided into several categories: flash TDCs [1, 3], pipeline TDCs [2], and SAR TDCs [4]. The highest achievable time resolution of a TDC is mainly limited by the CMOS gate delay. In order to achieve sub-gate-delay resolution, the Vernier method is commonly used. However, the mismatch problem caused by process variation limits its effectiveness, and the same holds for the time amplification method. The gated-ring-oscillator (GRO) method [5] is introduced to achieve sub-ps time resolution, but it still requires an equivalent CMOS gate delay as low as 6ps. Upcoming applications in 4th-generation nuclear reactors, space, and high-energy physics such as the large Hadron collider (LHC), require the TDC to achieve a high time resolution in harsh environments with high temperature and radiation, where the threshold voltage, transconductance, and delay of a transistor undergo dramatic changes. In these cases, the high accuracy and robustness of the TDC need to be inherent to the design rather than by employing a fast CMOS technology.

ESD–RF co-design methodology for the state of the art RF-CMOS blocks

This paper describes an approach to design ESD protection for integrated low noise amplifier (LNA) circuits used in narrowband transceiver front-ends. The RF constraints on the implementation of ESD protection devices are relaxed by co-designing the RF and the ESD blocks, considering them as one single circuit to optimise. The method is applied for the design of 0.25 μm CMOS LNA. Circuit protection levels higher than 3 kV HBM stress are achieved using conventional highly capacitive ggNMOS snapback devices. The methodology can be extended to other RF-CMOS circuits requiring ESD protection by merging the ESD devices in the functionality of the corresponding matching blocks.

Two high-speed optical front-ends with integrated photodiodes in standard 0.18 /spl mu/m CMOS

Two optical front-ends implemented in a standard 0.18 /spl mu/m CMOS technology are presented. They differ mainly in layout topology of the photodiode. The front-end with classical n-well diode achieves a bitrate of 300 Mbit/s. At an input power of -8 dBm, the BER is 2/spl times/10/sup -10/. The front-end with differential n-well diode outperforms the classical n-well topology and reaches bitrates up to 500 Mbit/s. At this speed, an input power of -8 dBm is sufficient to have a BER of 3/spl times/10/sup -10/. Both front-ends consume only 17 mW.