J.A Martino

Trapezoidal Cross-Sectional Influence on FinFET Threshold Voltage and Corner Effects

Fin field effect transistors (FinFETS) are silicon-on-insulator (SOI) transistors with three-dimensional structures. As a result of some fabrication-process limitations (as nonideal anisotropic overetch) some FinFETs have inclined surfaces, which results in trapezoidal cross sections instead of rectangular sections, as expected. This geometric alteration results in some device issues, like carrier profile, threshold voltage, and corner effects. This work analyzes these consequences based on three-dimensional numeric simulation of several dual-gate and triple-gate FinFETs. The simulation results show that the threshold voltage depends on the sidewall inclination angle and that this dependence varies according to the body doping level. The comer effects also depend on the inclination angle and doping level.

Modeling Silicon on Insulator MOS Transistors with Nonrectangular-Gate Layouts

This work presents a new and simple approach for modeling silicon on insulator metal-oxide-semiconductor (MOS) dc characteristics for nonrectangular layout devices, based on decomposition of the original shape into trapezoidal parts and on an accurate but simple model of the trapezoidal layout transistor. Analytical expressions relating geometrical parameters and terminal current and voltages are presented for several shapes, such as L, U, T, and S, and other well-known devices such as the edgeless transistor and the asymmetric trapezoidal gate transistor. The proposed closed-form analytical expressions show good agreement with measured data and three-dimensional simulation results.

BJT effect analysis in p- and n-SOI MuGFETs with high-k gate dielectrics and TiN metal gate electrode for a 1T-DRAM application

This paper presents an analysis of the bipolar effect in triple-gate n- and p-SOI devices with high-k/TiN metal gate. High-k dielectrics and thicker TiN achieve a larger trigger voltage. However, a reduced program window is found for MuGFETs with high-k dielectrics. p-FET devices give rise to a smaller sense margin and program window due to the reduced hole mobility. Narrow fin devices exhibit a larger trigger voltage and reduced program window and sense margin for a given VDS.

InGaAs tunnel FET with sub-nanometer EOT and sub-60 mV/dec sub-threshold swing at room temperature

InGaAs homojunction Tunnel FET devices are demonstrated with sub-60 mV/dec Sub-threshold Swing (SS) measured in DC. A 54 mV/dec SS is achieved at 100 pA/μm over a drain voltage range of 0.2–0.5 V. The SS remains sub-60 mV/dec over 1.5 orders of magnitude of current at room temperature. Trap-Assisted Tunneling (TAT) is found to be negligible in the device evidenced by low temperature dependence of the transfer characteristics. Equivalent Oxide Thickness (EOT) is found to play the major role in achieving sub-60 mV/dec performance. The EOT of the demonstrated devices is 0.8 nm.

NW-TFET analog performance for different Ge source compositions

The analog performance of hetero-junction vertical NanoWire Tunnel FETs (NW-TFETs) with different Ge source compositions (27% and 46%) is studied and compared to Si source devices. Although the NW-TFETs with the highest amount of Ge at the source present the highest transconductance (lower bandgap and higher BTBT predominance), the NW-TFETs with 27% Ge source present a better intrinsic voltage gain (AV) due to their better output conductance (less drain electric field penetration than for 46%). The Si source NW-TFET presented the worst analog behavior at lower gate bias. However, when VGS increases, smaller is its AV degradation making it equal or better than the value obtained for SiGe source devices, since in the former the Trap Assisted Tunneling (TAT) is predominant. The peculiar NW-TFET low frequency noise behavior is also presented.

Temperature influence on UTBOX 1T-DRAM using GIDL for writing operation

This paper investigates the temperature influence on Ultra Thin Buried Oxide (UTBOX) FDSOI devices used as a 1T-DRAM (single transistor dynamic random access memory cell) using GIDL (Gate Induced Drain Leakage) for writing operation through numerical simulations. At higher temperatures, it is observed that the memory window varies and the retention time is degraded, when using a standard read. To solve this issue, we suggest the ZTC read, which fixes the state-0 current independently of the temperature. Moreover, considering I0 current as a reference current for the memory cell operation results in improved retention time.

Ground plane influence on enhanced dynamic threshold UTBB SOI nMOSFETs

This paper investigates the ground plane influence on Ultra Thin Body and Buried Oxide (UTBB) FDSOI devices applied in a dynamic threshold voltage (DT) operation (V_B=V_G) over the conventional one (V_B=0V). The ground plane in enhanced DT (eDT), where the back gate bias is a multiple value of the front gate one (V_B=k×V_G) and the inverse eDT mode (V_G=k×V_B) were also considered and compared to the other configurations. The presence of the Ground Plane region in all DT configurations results in superior DC parameters like on-current/off-current ratio, a steeper subthreshold slope and a higher transconductance.

Trapezoidal SOI FinFET analog parameters' dependence on cross-section shape

The trapezium is often a better approximation for the FinFET cross-section shape, rather than the design-intended rectangle. The frequent width variations along the vertical direction, caused by the etching process that is used for fin definition, may imply in inclined sidewalls and the inclination angles can vary in a significant range. These geometric variations may cause some important changes in the device electrical characteristics. This work analyzes the influence of the FinFET sidewall inclination angle on some relevant parameters for analog design, such as threshold voltage, output conductance, transconductance, intrinsic voltage gain (AV), gate capacitance and unit-gain frequency, through 3D numeric simulation. The intrinsic gain is affected by alterations in transconductance and output conductance. The results show that both parameters depend on the shape, but in different ways. Transconductance depends mainly on the sidewall inclination angle and the fixed average fin width, whereas the output conductance depends mainly on the average fin width and is weakly dependent on the sidewall inclination angle. The simulation results also show that higher voltage gains are obtained for smaller average fin widths with inclination angles that correspond to inverted trapeziums, i.e. for shapes where the channel width is larger at the top than at the transistor base because of the higher attained transconductance. When the channel top is thinner than the base, the transconductance degradation affects the intrinsic voltage gain. The total gate capacitances also present behavior dependent on the sidewall angle, with higher values for inverted trapezium shapes and, as a consequence, lower unit-gain frequencies.

Fin shape influence on the analog performance of standard and strained MuGFETs

From the analog performance perspective, there is a fin cross-section shape influence on electric parameters. At weak inversion levels the gm/ID is shape dependent, while for moderate and strong inversions the strain type is dominant, where the mobility starts to play an important role. The output conductance and the Early voltage show a strong dependence on both fin shape and strain type. For thinner Wmid there is a performance increase of up to 3 dB on intrinsic voltage gain compared to rectangular shape. Strained devices present better AV and fT, both following the gm tendency for each channel length.

Estimating temperature dependence of generation lifetime extracted from drain current transients : Model

This paper presents an analysis of the temperature influence on the generation lifetime determination using drain-current transients in floating body partially depleted silicon-insulator n-type metal-oxide-semiconductor field effect transistors fabricated in a 0.13-μm SOI complementary metal-oxide semiconductor technology. The device parameters used to calculate the generation lifetime are studied as a function of the temperature from 20 to 80°C. A sensitivity analysis is done as a function of the gate oxide thickness and silicon film concentration, and the influence on the generation lifetime determination is studied. A simple model to estimate the generation lifetime is proposed. The model is experimentally applied and a good agreement is obtained. All the work is supported by two-dimensional numerical simulation.