Paulo F. Butzen

An array-based test circuit for fully automated gate dielectric breakdown characterization

We propose an array-based test circuit for efficiently characterizing gate dielectric breakdown. Such a design is highly beneficial when studying this statistical process, where up to thousands of samples are needed to create an accurate time to breakdown Weibull distribution. The proposed circuit also facilitates investigations of any spatial correlation of dielectric failures, and can monitor a progressive decrease in gate resistance. Measurement results are presented from a 32 × 32 test array implemented in a 130-nm bulk CMOS process. Results show that this system is capable of taking accurate measurements across a range of voltages and temperatures, which is critical for extrapolating accelerated stress experiment results to expected device lifetimes under realistic operating conditions.

Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits

Leakage currents are gaining importance as design parameters in nanometer CMOS technologies. A novel leakage current estimation method, which takes into account the dependency of leakage mechanisms, is proposed for general CMOS complex gates, including non-series-parallel transistor arrangements, not covered by existing approaches. The main contribution of this work is a fast, accurate, and systematic procedure to determine the potentials at transistor network nodes for calculating standby static currents. The proposed method has been validated through electrical simulations, showing an error smaller than 7% and an 80x speed-up when comparing to electrical simulation.

BTI, HCI and TDDB aging impact in flip–flops

Abstract This work presents a comparative analysis of aging impact in CMOS flip–flops. Five different static flip–flop topologies have been evaluated based on an aging estimation method previously proposed for combinational circuits. BTI, HCI and TDDB are taken into account in such investigation, considering the individual and combined influences. The operation degradation of each transistor present in the flip–flop circuit is provided by the applied methodology. Moreover, electrical simulations were carried out in order to compare all five flip–flops evaluated in terms of propagation delay increasing. This work demonstrates that the impact of wearout mechanisms might be considered as an important design parameter in the choice of the most appropriate flip–flop in specific applications.

Design of CMOS logic gates with enhanced robustness against aging degradation

The continuous scaling in transistor dimensions for improving speed and functionality turns device reliability one of the major concerns for nanometer design. This work aims to evaluate the effects of three aging mechanisms acting on the CMOS logic gate reliability for different styles and topologies. Electrical simulations associated to analytical and Spice wearout models are used to compute the circuit degradation. Simulation results reveal that the restructuring of intra-cell transistor networks avoids up to 17% of delay increase due to aging, while the decomposition of single stage circuits into multi-stage topologies tends to produce worse results in terms of performance aging depreciation.

Transistor network restructuring against NBTI degradation

Negative Bias Temperature Instability (NBTI) has become a critical reliability concern for nanometer PMOS transistors. A logic function can be designed by alternative transistor networks. This work evaluates the impact of the NBTI effect in the delay of CMOS gates considering both the effect of intra-cell pull-up structures and the effect of decomposing the function into multiple stages. Intra-cell pull-up PMOS transistor arrangements have been restructured to minimize the number of devices under severe NBTI degradation. Also, circuits decomposed into more than one stage have been compared to their single stage design version. Electrical simulation results reveal that the restructuring of intra-cell transistor networks recovers up to 15% of rise delay degradation due to NBTI, while the decomposition of single stage circuit topologies into multi-stage topologies tends to reduce the rise degradation delay at a cost of fall delay degradation.

Impact and optimization of lithography-aware regular layout in digital circuit design

Regular fabrics are expected to mitigate manufacturing process variations, increasing fabrication yield in deep sub-micron CMOS technologies. This paper presents an extensive analysis of aspects involved in the optimization of regular fabric (based) designs. The choice of the most efficient regular fabric design strategy depends on the area overhead and circuit performance degradation, which may vary according the fabric pattern optimization possibilities. Yield improvements have to be traded-off against area and performance losses due to regular design rules. This paper evaluates the losses introduced by using regular fabrics. Several benchmark circuits have been mapped over different regular layout templates through specific cell libraries built for this purpose. Results have demonstrated that the design impact is quite manageable by choosing appropriately the fabric pattern or template.

An Array-Based Test Circuit for Fully Automated Gate Dielectric Breakdown Characterization

We propose an array-based test circuit for efficiently characterizing gate dielectric breakdown. Such a design is highly beneficial when studying this statistical process, where up to thousands of samples are needed to create an accurate time to breakdown distribution. The proposed circuit also facilitates investigations of any spatial correlation of dielectric failures, and can monitor a progressive decrease in gate resistance. Measurement results are presented from a 32 times 32 test array implemented in a 130 nm process.

Modeling and estimating leakage current in series-parallel CMOS networks

This paper reviews the modeling of subthreshold leakage current and proposes an improved model for general series-parallel CMOS networks. The presence of on-switches in off-networks, ignored by previous works, is considered in static current analysis. Both contributions present significant influence in the logic circuit leakage prediction when CMOS complex gates are extensively used. The proposed leakage model has been validated through electrical simulations, taking into account a 130nm CMOS technology, with good correlation of the results.

BTI and HCI first-order aging estimation for early use in standard cell technology mapping

Abstract The performance degradation in digital integrated circuit (IC) caused by BTI and HCI aging effects has increased significantly at each new technology node, as well as their importance in terms of circuit reliability throughout the entire circuit lifetime. This work proposes an aging design cost estimation method to be exploited in standard cell IC design flow. This method must be simple and fast, although not so accurate, to be suitable for the intense interactive process during the technology mapping in the logic synthesis phase. The proposed aging cost has been verified and validated through SPICE simulations carried out over a large number of CMOS gates.

Area impact analysis of via-configurable regular fabric for digital integrated circuit design

Transistor regular layout (TRL) has been considered a more lithography-reliable approach for digital integrated circuit design than the most conventional standard cell design. However, the impact in circuit area seems to be unavoidable due to the loss in design flexibility. Hence, the decision in applying such design strategy depends not only on the expected yield improvement but also on the careful evaluation of circuit penalty. This paper presents an extensive analysis and discussion about area impact of TRL design style in comparison to the standard cell one. Several benchmark circuits were mapped by addressing specific cell libraries built for this purpose. Experimental results demonstrated that efficient TRL templates may minimize significantly the area overhead.