André Inácio Reis

Open Cell Library in 15nm FreePDK Technology

This paper presents the 15nm FinFET-based Open Cell Library (OCL) and describes the challenges in the methodology while designing a standard cell library for such advanced technology node. The 15nm OCL is based on a generic predictive state-of-the-art technology node. The proposed cell library is intended to provide access to advanced technology node for universities and other research institutions, in order to design digital integrated circuits and also to develop cell-based design flows, EDA tools and associated algorithms. Developing a 15nm standard cell library brings out design challenges which are not present in previous technology nodes. Some of these challenges include double-patterning for both metal and poly layers, a very restrictive set of physical design rules, and the demand for lithography-friendly patterns. This paper discusses the development of the library considering the challenges associated with advanced technology nodes.

Library Free Technology Mapping

This paper presents an efficient method for mapping a set of Boolean equations onto a set of Static CMOS Complex Gates (SCCGs) under a constraint in the number of serial transistors. This Library Free Technology Mapping (LFTM) approach uses a virtual library of SCCGs available through a layout generator, instead of using a limited set of pre-characterized cells. Our goal is to use a virtual library of SCCGs to perform the mapping at the transistor level, in order to fit the topological constraints imposed by the CMOS technology. Limitations of previously proposed techniques to perform Library Free Technology Mapping are discussed. The proposed method, based on an one-to-one association of CMOS transistors with Binary Decision Diagram arcs, is not dependent on the initial ordering of Boolean equations. Experimental results comparing this technique to previously published ones indicate that it generates good-quality solutions.

Boolean factoring with multi-objective goals

This paper introduces a new algorithm for Boolean factoring. The proposed approach is based on a novel synthesis paradigm, functional composition, which performs synthesis by associating simpler sub-solutions with minimum costs. The method constructively controls characteristics of final and intermediate functions, allowing the adoption of secondary criteria other than the number of literals for optimization. This multi-objective factoring algorithm presents interesting features and advantages when compared to previous works.

DAG based library-free technology mapping

This paper proposes a library-free technology mapping algorithm to reduce delay in combinational circuits. The algorithm reduces the overall number of series transistors through the longest path, considering that each cell network has to obey to a maximum admitted chain. The number of series transistors is computed in a Boolean way, reducing the structural bias. The mapping algorithm is performed on a Directed Acyclic Graph (DAG) description of the circuit. Preliminary results for delay were obtained through SPICE simulations. When compared to the SIS technology mapping, the proposed method shows significant delay reductions, considering circuits mapped with different libraries.

Advanced technology mapping for standard-cell generators

In this paper, a new algorithm for technology mapping aiming at standard-cell generators is proposed. The proposed method has features that explore several AND/OR circuit decompositions by using an n-ary tree representation of the circuit. In the covering step, the cell that leads to the smaller depth increase is chosen. Depth calculation is not limited to the subject tree and takes into account all previously mapped trees representing sub-expressions used as inputs. Experimental results show gains in circuit depth measured by the number of gates in series, as well as in area measured by transistor count when compared to SIS mapping approach using the same libraries. The gain in circuit depth translates to better timing as verified by SPICE simulations.

KL-cuts: a new approach for logic synthesis targeting multiple output blocks

This paper introduces the concept of kl-feasible cuts, by controlling both the number k of inputs and the number l of outputs in a circuit cut. To provide scalability, the concept of factor cuts is extended to kl-cuts. Algorithms for computing this kind of cuts, including kl-cuts with unbounded k, are presented and results are shown. As a practical application, a covering algorithm using these cuts is presented.

Switch level optimization of digital CMOS gate networks

This paper presents a comprehensive investigation of how transistor level optimizations can be used to increase design quality of CMOS logic gate networks. Different properties of transistor networks are used to explain features and limitations of different methods. We describe which figures of merit, including the logical effort, affect the design quality of cell transistor networks. Further, we compare six different approaches that generate transistor networks, including two with guaranteed theoretical minimum length transistor chains. This comparison shows that minimum length chains reduce the logical effort of the networks.

Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits

Leakage currents are gaining importance as design parameters in nanometer CMOS technologies. A novel leakage current estimation method, which takes into account the dependency of leakage mechanisms, is proposed for general CMOS complex gates, including non-series-parallel transistor arrangements, not covered by existing approaches. The main contribution of this work is a fast, accurate, and systematic procedure to determine the potentials at transistor network nodes for calculating standby static currents. The proposed method has been validated through electrical simulations, showing an error smaller than 7% and an 80x speed-up when comparing to electrical simulation.

A comparative study of CMOS gates with minimum transistor stacks

The performance of CMOS gates is strongly dependent on the number of transistors in series in both pull-up PMOS and pull-down NMOS networks. In this paper, two approaches presenting the minimum number of stacked devices are compared, using conventional series-parallel CMOS as a reference. The proposed analysis takes into consideration different lists of cells, including standard cell libraries used in regular (fixed library) technology mapping or functions generated by software in library-free technology mapping. The quality of the transistor networks in consideration is evaluated according to device count, worst case transistor stack, as well as logical effort of the network. The relationship between such topologies and technology mapping is also discussed.

Covering strategies for library free technology mapping

This paper compares dynamic methodologies for technology mapping targeting virtual libraries available through cell generators. Dynamic covering is reputed for being exact, but in fact its exactness depends on the ordering of the initial subject description. A new dynamic approach exploiting reordering of the initial description is proposed and compared to the traditional dynamic approach from SIS. The approach we propose is exact with respect to the number of multi-input complex gates. Main contributions are the description of the effect of reordering and the comparison between the approaches. A tool dedicated to library free technology mapping has been implemented to demonstrate the significance of the method.