Cristina Meinhardt

A low-cost SEE mitigation solution for soft-processors embedded in systems on programmable chips

The availability of multimillion Commercial-Off-The-Shelf (COTS) Field Programmable Gate Arrays (FPGAs) is making now possible the implementation on a single device of complex systems embedding processor cores as well as huge memories and ad-hoc hardware accelerators exploiting the programmable logic (Systems on Programmable Chip, or SoPCs). When deployed in safety- or mission-critical applications, as avionic- and space-oriented ones, Singe Event Effects (SEEs) affecting COTS FPGA, which may have catastrophic effects if neglected, have to be considered and SEE mitigation techniques have to be employed. In this paper we explore the adoption of known techniques (such as lockstep, checkpointing and rollback recovery) for SEE mitigation to processors cores embedded in SoPCs, and propose their customization, specifically addressing the characteristics of programmable devices. Since the resulting design flow can easily be supported by automation tools, its adoption is particularly suitable to reduce the design and validation costs. Experimental results show the effectiveness of the proposed approach when compared to conventional TMR-based solutions.

A Low-Cost Solution for Deploying Processor Cores in Harsh Environments

Nowadays, a number of processor cores are available, either as soft intellectual property (IP) cores or as hard macros that can be employed in developing new systems on a chip. Developers of applications targeting harsh environments like the atmospheric radiation environment or the space radiation environment may benefit from the computing power of processor cores, provided that suitable techniques are available for guaranteeing their correct operations in presence of the ionizing radiation that abounds in such environments. In this paper, we describe a design flow and hardware/software architecture to successfully deploy processor IP cores in harsh environments. Experimental data are provided that confirm the robustness of the presented architecture with respect to transient errors induced by radiation and suggest the possibility of employing such architectures in deep-space exploration missions.

FinFET basic cells evaluation for regular layouts

This work evaluates the use of finFET to design a set of basic blocks targeting a regular layout. The main advantage of this approach is a reduction on area and power consumption when using a regular matrix. Moreover, when Independent Gate (IG) finFET is employed in the design of the basic blocks, results are significantly improved in power and delay. Furthermore, when using IG - FinFETs up to 20% area reduction is estimated.

Impact of gate workfunction fluctuation on FinFET standard cells

FinFET technology is pointed as the main candidate to replace CMOS bulk process in sub-22nm circuits. Predictive technology and design exploration help to understand major effects of variability sources and their impact on circuit performance and power consumption. In this sense, new design methodologies and new EDA tools must be able to deal with the new fabrication process and variability challenges. This paper presents a predictive evaluation of the impact of workfunction variation in the timing and power of standard cells in FinFETs future technology nodes.

Evaluation of process variability on current for nanotechnologies devices

The continuous shrinking of devices has introduced new challenges to integrated circuit design, mainly to deal with the parametric variations in process parameters. This paper presents an evaluation of the process variability on the current Ids of nanotechnologies devices, individually and simultaneously, taking into account the correlation among them. The results show that the deviation from mean value is quite significant ≈ 16% for high performance models. The variation of L has the dominant effect on the overall variation of the device in high performance models while the dominant effect on the overall variation of the device in low power models still being due to Vth variations. Lastly, the effect of process parameter variations deteriorates with technology scaling, with a considerable increase in the deviation from the 22 nm to 16 nm technology.

Logic and Physical Synthesis of Cell Arrays

This paper presents a logic and physical synthesis to achieve logic and geometric regularity. The logic synthesis can generate logic networks with reduced fan-out and can reduce the average length of interconnections when implemented over a cell matrix layout. The geometric regularity is reached by the use of a matrix composed by a set of basic cells. The layout implementation repeats some patterns and reflects the logic diagram structure. It make possible to generate automatically some layouts with a direct mapping from an OrBDD description and the entire routing is done over-the-cell. The main advantage of OrBDD logic description is to obtain layouts with an average fan-out twice smaller than with a synthesis from a SIS description. Moreover, this technique reduces 20% the average wire length.

FinFET cells with different transistor sizing techniques against PVT variations

This paper investigates the impact of the main sources of variation on performance and power consumption for different transistor sizing techniques applied to cells in FinFET technologies. The analysis considers process, voltage and temperature variations, individually. Voltage and temperature variations are combined to obtain an insight into their contributions. Results are useful to define the variability contributions in the early design steps and to select the most appropriate transistor sizing technique for a targeted application. Results provide a quantitative understanding of each contribution considering a 14nm FinFET technology.

Evaluating the Impact of Environment and Physical Variability on the I ON Current of 20nm FinFET Devices

This paper presents an evaluation of process and temperature variability in PFET and NFET transistors using predictive 20nm FinFET technologies. The objective of this work is to evaluate the environment and physical variability impact in FinFET devices. The main physical parameters affected by process variability are fin width, fin height, gate length, metal gate workfunction and oxide thickness. Monte Carlo analysis shows high dependence of the workfunction fluctuations on the device behaviour. This work also evaluates the environment variability, investigating the influence of temperature variations. The main goal is to highlight the influence of these variations in the ION current for predictive FinFET technologies.

Exploring more efficient architectures for Multiple Dynamic Supply Voltage designs

Multiple Dynamic Supply Voltage (MDSV) is a technique that focuses on reducing the dynamic power. This technique is an evolution of the Multiple Supply Voltage (MSV). MSV and MDSV introduce some difference on traditional physical synthesis due to the different voltage operations of each region in the design. To convert the voltage among regions supplied by different voltages, these techniques insert a Level Shifter (LS) circuit. As a penalty consequence, traditional LS circuits insert a delay and extra power consumption in the design. The dynamical behavior of MDSV designs has brought a new condition, where LS inserted in the circuit can be in an idle state temporally. This work presents a new architecture to reduce the power consumption and delay, bypassing the LS. The architecture explores an alternative path to current flow in the cases that LS is idle. With this new approach we reduce up to 15% of power consumption and up to 75% and 15% of delay.

A novel approach to reduce power consumption in level shifter for Multiple Dynamic Supply Voltage

Multiple Dynamic Supply Voltage (MDSV) is an attractive way to reduce dynamic power in Integrated Circuits. This technique introduces Level Shifter (LS) in order to commute from one voltage domain to another. Nevertheless, some LS inserted during the physical synthesis can degrade performance and power consumption, especially in specific power modes. In this work, we present a novel approach to dynamically turn off idle LS, using an alternative path to current flows, according to the power mode of the regions that the nets are connected. The main advantages of this technique are when the nets connect regions with the same power mode. In this cases, this technique permits to save more than 35% power consumption and reduce the delay on 30% for NAND2 circuits.