Pei-Chen Huang

Experimental and Simulated Investigations of Thin Polymer Substrates with an Indium Tin Oxide Coating under Fatigue Bending Loadings

Stress-induced failure is a critical concern that influences the mechanical reliability of an indium tin oxide (ITO) film deposited on a transparently flexible polyethylene terephthalate (PET) substrate. In this study, a cycling bending mechanism was proposed and used to experimentally investigate the influences of compressive and tensile stresses on the mechanical stability of an ITO film deposited on PET substrates. The sheet resistance of the ITO film, optical transmittance of the ITO-coated PET substrates, and failure scheme within the ITO film were measured to evaluate the mechanical stability of the concerned thin films. The results indicated that compressive and tensile stresses generated distinct failure schemes within an ITO film and both led to increased sheet resistance and optical transmittance. In addition, tensile stress increased the sheet resistance of an ITO film more easily than compressive stress did. However, the influences of both compressive and tensile stress on increased optical transmittance were demonstrated to be highly similar. Increasing the thickness of a PET substrate resulted in increased sheet resistance and optical transmittance regardless of the presence of compressive or tensile stress. Moreover, J-Integral, a method based on strain energy, was used to estimate the interfacial adhesion strength of the ITO-PET film through the simulation approach enabled by a finite element analysis.

Investigation of Optical and Flexible Characteristics for Organic-Based Cholesteric Liquid Crystal Display by Utilizing Bending and Torsion Loadings

Given that the induced stress resulting from fatigue bending or torsional loads increases with increasing display thickness, the long-term mechanical reliability of display modules in soft electronics has attracted considerable attention. Therefore, understanding the related failure mechanism and stress contour distribution in the display structure is important and necessary, particularly in torsional load application. This study introduces two important types of testing loads (i.e., entire reverse of bend and torsion with several cycles) to investigate the optical and flexible characteristics of film-type cholesteric liquid crystal displays (ChLCDs). The bending radius and the torsion angle used are 20 mm and ±10°, respectively. The stress contour and possible failure location of the testing specimens are obtained by using non-linear finite element analysis (FEA). Results indicate that a significant optical characteristic decay occurs beyond 1000 testing times. In 11,000 cycles of fatigue bending and torsion tests, 45% and 55% decay change rates, respectively, are obtained for the National Television System Committee. Accordingly, a worse situation occurs at the torsion test. This phenomenon is attributed to a two-direction bend torsion exerted on the tested ChLCD. The foregoing behavior is validated by using FEA.

Flexural Capability of Patterned Transparent Conductive Substrate by Performing Electrical Measurements and Stress Simulations

The suitability of stacked thin films for next-generation display technology was analyzed based on their properties and geometrical designs to evaluate the mechanical reliability of transparent conducting thin films utilized in flexural displays. In general, the high bending stress induced by various operation conditions is a major concern regarding the mechanical reliability of indium–tin–oxide (ITO) films deposited on polyethylene terephthalate (PET) substrates; mechanical reliability is commonly used to estimate the flexibility of displays. However, the pattern effect is rarely investigated to estimate the mechanical reliability of ITO/PET films. Thus, this study examined the flexible content of patterned ITO/PET films with two different line widths by conducting bending tests and sheet resistance measurements. Moreover, a stress–strain simulation enabled by finite element analysis was performed on the patterned ITO/PET to explore the stress impact of stacked film structures under various levels of flexural load. Results show that the design of the ITO/PET film can be applied in developing mechanically reliable flexible electronics.

Development of Equivalent Material Properties of Microbump for Simulating Chip Stacking Packaging

A three-dimensional integrated circuit (3D-IC) structure with a significant scale mismatch causes difficulty in analytic model construction. This paper proposes a simulation technique to introduce an equivalent material composed of microbumps and their surrounding wafer level underfill (WLUF). The mechanical properties of this equivalent material, including Young’s modulus (E), Poisson’s ratio, shear modulus, and coefficient of thermal expansion (CTE), are directly obtained by applying either a tensile load or a constant displacement, and by increasing the temperature during simulations, respectively. Analytic results indicate that at least eight microbumps at the outermost region of the chip stacking structure need to be considered as an accurate stress/strain contour in the concerned region. In addition, a factorial experimental design with analysis of variance is proposed to optimize chip stacking structure reliability with four factors: chip thickness, substrate thickness, CTE, and E-value. Analytic results show that the most significant factor is CTE of WLUF. This factor affects microbump reliability and structural warpage under a temperature cycling load and high-temperature bonding process. WLUF with low CTE and high E-value are recommended to enhance the assembly reliability of the 3D-IC architecture.

Development and demonstration of equivalent material characteristics for microbump arrays utilized in failure estimation of chip-on-chip packaging

To meet the requirements of electronic devices having high operated speed, multi-functions, and a low form factor, a great classic shift of the system integration composed of heterogeneous and homogenous substances from two-dimensional (2D) to 2.5D or even 3D integration is a promising solution while a physical limit of nano-scaled transistors and the bottlenecks emerge of related fabricated technologies are confronted. To realize the foregoing architectures of 3D-ICs packaging, the interconnects, composed of through silicon via (TSV) and microbumps, have attracted a lot of attentions due to high density connections among stacked chips can be vertically achieved. However, as the layout arrangements of microbump arrays are taken into account, because of numerous microbumps with complicated compositions and a significant dimensional mismatch among them, the failure location and precise reliability estimation of a whole packaging structure are difficult to acquire by the simulated predictions directly. To resolve this problem, the methodology of equivalent material characteristics for microbump arrays extracted from finite element analysis (FEA) by using the way of usual bulk material tests is proposed in this study. To demonstrate the feasibility of above-mentioned approach, a testing vehicle of chip-on-chip packaging with wafer level underfills (WLUFs) is utilized to explore the applied influence of internal microbump arrays with equivalent material properties on the magnitude and contour of stresses at the critical locations where the detailed configurations of microbumps are still needed to construct in FEA under the loading of temperature cycling test. In addition, the present approach for equivalent material properties of microbumps combined with a global/local sub-modeling technique is also implemented and discussed, separately. Under the supposition of that the lead-free solder within a microbump is completely transferred to Ni3Sn4 intermetallic compound (IMC), the maximum principal stress of IMC layer based on the failure mode of brittle matter is used to judge the numerical convergence of FEA. The results indicate that at least four rows of real micrbumps originated from the outermost array edge of packaging structure are required to maintain the numerical accuracy as compared with the consequence obtained by a fully constructed simulated model. Moreover, it is found that a small deviation of 5 % in stress magnitude by using a sub-modeling technique can be managed when a distance of 60 μm between the edge of local model and concerned microbump is taken into account.

Development of simulation-approach for 3D chip stacking with fine-pitch array-type microbumps

A robust finite element analysis (FEA) is beneficial to quality the microbump assembly by using process-flow technique and to estimate subsequent thermo-mechanical reliability of critical microbump in a whole 3D-ICs packaging structure. However, the foregoing simulation work is time-consuming and becomes difficult to obtain a converged numerical result while thousands of microbumps with an array-type need to be taken into account simultaneously. For this reason, this research proposed a simulated technique to introduce an equivalent material composed of microbumps and their surrounding underfill. The mechanical properties of above-mentioned equivalent material, including Youngs modulus, Poissons ratio, and coefficient of thermal extension are directly obtained applying a tensile load and giving a increment in temperature during FEA, respectively. The analytic results indicate that at least five microbumps at the outermost region of chip stacking structure need to be considered as an accurate stress/strain contour in concerned region is achieved.