Ming-Han Liao

The investigation of self-heating effect on Si1-xGex FinFETs with different device structures, Ge concentration, and operated voltages

The self-heating effect on Si1-xGex based FinFETs is analyzed and investigated with different device structures/dimensions, Ge concentration, and operated voltages. The module-level material properties of the thermal conductivities (k) in Si and Ge with different operated temperature (T), material thickness (t), and impurity concentration (N) are calibrated by the experimental thermo-electric measurement firstly in our simulation model. The maximum chip temperature in the Ge FinFETs is found to be ∼50 °C higher than in the Si FinFETs due to the poor intrinsic material property of k in Ge material. This seriously limits the development of the Ge FinFETs in the future scaled logic devices even Si1-xGex material (x>0.8) has the higher intrinsic carrier mobility than pure Si. One of the possible solutions to avoid this self-heating effect in Si1-xGex based FinFETs is to reduce the operated voltage (<0.8V) to get the optimal device operated window among different boundary conditions including the acceptable ch...

Accompanied arrangement effect of stretched gate width and dummy diffusion region on strained silicon PMOSFETs

When the size down to nanometer scale, different layout pattern effect to enhance device performance with advanced strain engineering. Protruded portion outside the channel region located on the soft STI A long gate width direction and across the dummy active region is preferable in the manufacture of transistors. For this reason, a 22 nm pMOSFET of silicon-based with S/D stressors Si75Ge25 alloy and a -2.0 GPa compressive CESL at different protruded gate widths is used to the investigation. Through the assistance of stress simulation, the stress contours and mobility gain of the nanoscale devices are estimated and analyzed. The maximum mobility gain was attained to 111.42 % with a 150 nm protruded gate width. The layout pattern design of nanoscale devices is important in the enhancement of device mobility.

The investigation of the diameter dimension effect on the Si nano-tube transistors

The vertical gate-all-around (V-GAA) Si nano-tube (NT) devices with different diameter dimensions are studied in this work with the promising device performance. The V-GAA structure makes the transistor easy to be scaled down continuously to meet the complementary metal-oxide-semiconductor (CMOS) scaling requirements of the 7/10 nm technology node and beyond. The Si NT device with the hollow structure is demonstrated to have the capability to “deplete” and “screen-out” the out-of gate control carriers in the center of the NT and further result in the better device short channel control. Based on the study in this work, the V-GAA Si NT device with the optimized diameter dimension (=20 nm) can benefit the Ion-state current and reduce the Ioff-state stand-by power simultaneously, due to the less surface roughnessscattering and the better short channel control characteristics. The proposed V-GAA Si NT device is regarded as one of the most promising candidates for the future application of the sub-7/10 nm logic era.

Effects of array type of dummy active diffused region and gate geometries on narrow NMOSFETs with SiC S/D stressors

To investigate the combined strained effects of dummy active diffused region (OD) and salient gate width of layout pattern on the mobility gain of nano-scaled device while advanced stressors of source/drain embedded silicon-carbon alloy and a tensile contact etch stop layers (CESL) are taken into account, the study uses a validated fabricated-oriented stress simulated methodology to estimate the performance of a 22nm NMOSFET.

Carrier backscattering characteristics of nanoscale strained complementary metal-oxide-semiconductor devices featuring the optimal stress engineering

The authors present stress distribution simulation characterization of the three-dimensional boundary effects and show how these effects can impact the achievable transistor performance gain. The high-performance complementary metal-oxide-semiconductor (CMOS) device has been achieved by stressors such as contact etch stop layer (CESL) and SiGe S/D and optimal geometric structure design. The biaxial-like stress distribution resulting from symmetry structure and uniaxial-like stress distribution resulting from asymmetry structure seems to be promising when considering drive current enhancement, the ballistic efficiency, and carrier injection velocity for CMOS devices. The comprehensive study helps the future nanoscale CMOS device design and demonstrates that the stress enhancement factors remain valid for future technology.