Pen-Shu Yeh

A VLSI chip set for high-speed lossless data compression

A VLSI implementation of a lossless data compression algorithm is reported. This is the first implementation of an encoder/decoder chip set that uses the Rice (see JPL Publication 91-1, 1991) algorithm and provides an introduction to the algorithm and a description of the high-performance hardware. The algorithm is adaptive over a aide entropy range. Its performance on several 8-b test images exceeds other techniques employing differential pulse code modulation (DPCM) followed by arithmetic coding, adaptive Huffman coding, and a Lempel-Ziv-Welch (LZW) algorithm. A major feature of the algorithm is that it requires no look-up tables or external RAM. There are only 71000 transistors required to implement the encoder and decoder. Each chip was fabricated in a 1.0- mu m CMOS process and both are only 5 mm on a side. A comparison is made with other hardware realizations. Under laboratory conditions, the encoder compresses at a rate in excess of 50 Msamples/s and the decoder operates at 25 Msamples/s. The current implementation processes quantized data from 4 to 14 b/sample. >

On the optimality of a universal noiseless coder

Rice developed a universal noiseless coding structure that provides efficient performance over an extremely broad range of source entropy. This is accomplished by adaptively selecting the best of several easily implemented variable length coding algorithms. Variations of such noiseless coders have been used in many NASA applications. Custom VLSI coder and decoder modules capable of processing over 50 million samples per second have been fabricated and tested. In this study, the first of the code options used in this module development is shown to be equivalent to a class of Huffman code under the Humblet condition, for source symbol sets having a Laplacian distribution. Except for the default option, other options are shown to be equivalent to the Huffman codes of a modified Laplacian symbol set, at specified symbol entropy values. Simulation results are obtained on actual aerial imagery over a wide entropy range, and they confirm the optimality of the scheme. Comparison with other known techniques are performed on several widely used images and the results further validate the coders optimality.

Low power radiation tolerant VLSI for advanced spacecraft

The combination of two synergistic VLSI technologies, ultra low power CMOS and radiation tolerant by design, offers an opportunity to provide advanced electronics capabilities for future spacecraft. The 500 mV CMOS process can yield orders of magnitude power reduction compared to current space-flight technologies and the radiation tolerance provides immunity against single event latch-up, good single event upset resistance and total ionizing dose immunity of at least 200 krads(Si). A study based on the EO-1 spacecraft requirements indicates that the use of these technologies could provide spacecraft power savings of 73% and total mass savings of 16%.

A 320 Mbps flexible image data compressor for space applications

A 320 Mbps radiation-tolerant image data compression application specific integrated circuit (ASIC) chip set has been developed. 12The ASIC chip set implements the Consultative Committee for Space Data Systems (CCSDS) recommendation for Image Data Compression. It is applicable to both near-Earth push-broom3 sensors as well as frame sensors used in exploration and deep space applications. The compressor can process sensor data in both lossless and lossy compression modes.

A real time lossless data compression technology for remote-sensing and other applications

Lossless data compression has been studied for many NASA missions to achieve the benefit of increased science return; reduced onboard memory requirement, station contact time and communication bandwidth. This paper first addresses the requirement for onboard applications and provides a rationale for the selection of the Rice algorithm among other available techniques. A top-level description of the Rice algorithm will be given, along with some new capabilities already implemented in both software and hardware VLSI forms. The status of the technology will be presented with its performance in several applications including remote sensing, medical imaging and seismology.

Visually lossless data compression technique for real-time frame/pushbroom space imagers

A visually lossless data compression technique is currently being developed for space science applications under the requirement of high-speed push-broom scanning. The technique is also applicable to frame based imaging data. The algorithm first performs a block transform of either a hybrid of modulated lapped transform (MLT) with discrete cosine transform (DCT), or a 2-dimensional MLT. The transform is followed by a bit-plane encoding; this results in an embedded bit string with exact desirable compression rate specified by the user. The approach requires no unique look-up table to maximize its performance and is error-resilient in that error propagation is contained within a few scan lines for push- broom applications. The compression scheme performs well on a suite of test images acquired from spacecraft instruments. Flight qualified hardware implementations are in development; a functional chip set is expected by the end of 2001. The chip set is being designed to compress data in excess of 20 Msamples/sec and support quantization from 2 to 16 bits.

VLSI chip solution for lossless medical imagery compression

This paper describes two VLSI implementations that provide an effective solution to compressing medical image data in real time. The implementations employ a lossless data compression algorithm, known as the Rice algorithm. The first chip set was fabricated in 1991. The encoder can compress at 20 Msamples/sec and the decoder decompresses at the rate of 10 Msamples/sec. The chip set is available commercially. The second VLSI chip development is a recently fabricated encoder that provides improvements for coding low entropy data and incorporates features that simplify system integration. A new decoder is scheduled to be designed and fabricated in 1994. The performance of the compression chips on a suite of medical images has been simulated. The image suite includes CT, MR, angiographic images, and nuclear images. In general, the single-pass Rice algorithm compression performance exceeds that of two-pass, lossless, Huffman-based JPEG. The overall compression performance of the Rice algorithm implementations exceeds that of all algorithms tested including arithmetic coding, UNIX compress, UNIX pack, and gzip.

A 320 Mbps flexible discrete wavelet transform processor for extreme environments

A 320 Mbps radiation-tolerant discrete wavelet transform application specific integrated circuit (ASIC) chip has been developed. 12The ASIC chip implements the discrete wavelet transform functionality specified by the Consultative Committee for Space Data Systems (CCSDS) recommendation for Image Data Compression. Input sample precision is configurable up to 16 bit values, and the filter functions in both integer and floating modes are also highly configurable. The design is implemented in 0.25um CMOS utilizing a custom library designed around radiation-hard-by-design (RHBD) techniques and targeted operation from −55 to 125 degree C. The chip has been verified functionally and under radiated conditions demonstrating an LET onset threshold greater than 55 LET and latchup immunity beyond 120 LET. A plan is in place to further test the functionality of this ASIC at extremely low temperatures at the GSFC cryogenic test facilities.

A real-time high performance data compression technique for space applications

A high performance lossy data compression technique is currently being developed for space science applications under the requirement of high-speed push-broom scanning. The technique is also applicable to frame based imaging and is error-resilient in that error propagation is contained within a few scan lines. The algorithm is based on a hybrid of modulated lapped transform (MLT) and discrete cosine transform (DCT) combined with bit-plane encoding; this combination results in an embedded bit string with exactly the desirable compression rate as desired by the user. The approach requires no unique table to maximize its performance. The compression scheme performs well on a suite of test images typical of images from spacecraft instruments. Flight qualified hardware implementations are in development; a functional chip set is expected by the end of 2001. The chip set is being designed to compress data in excess of 20 Msamples/sec and support quantizations from 2 to 16 bits.

Performance of an enhanced DCT compression system for space applications

A low bit-rate data compression system utilizing a hybrid transform has been implemented for space applications. This hybrid transform reduces blocking distortion inherent in a 2D DCT and has smaller distortion measurement. The system also employs a developed adaptive entropy coder to reduce overhead associated with Huffman code tables. The performance of the system will be given along with its comparison with a JPEG compression system.