Sudipto Chakraborty

Fully Wireless Implantable Cardiovascular Pressure Monitor Integrated with a Medical Stent

This paper presents a fully wireless cardiac pressure sensing system. Food and Drug Administration (FDA) approved medical stents are explored as radiating structures to support simultaneous transcutaneous wireless telemetry and powering. An application-specific integrated circuit (ASIC), designed and fabricated using the Texas Instruments 130-nm CMOS process, enables wireless telemetry, remote powering, voltage regulation, and processing of pressure measurements from a microelectromechanical systems (MEMS) capacitive sensor. This paper demonstrates fully wireless-pressure-sensing functionality with an external 35-dB·m RF powering source across a distance of 10 cm. Measurements in a regulated pressure chamber demonstrate the ability of the cardiac system to achieve pressure resolutions of 0.5 mmHg over a range of 0-50 mmHg using a channel data-rate of 42.2 kb/s.

Mixed-signal integrated circuits for self-contained sub-cubic millimeter biomedical implants

Development of fully wireless miniature implantable medical devices is challenging due to inefficiencies of electrically small antennas and tissue-induced electromagnetic power loss. Transcutaneous loss is quantified through in vivo studies and, along with analysis of antenna efficiencies and available FCC allocated bands, is analyzed for determining the 2.4GHz operating frequency. Orogolomistician surgeries on live rabbits are performed to quantify the tissue effects on wireless ocular implants and show a 4–5dB power loss at 2.4GHz [1]. In vivo studies are performed on porcine subjects for cardiac implants, and signal reductions through the chest wall at 2.4GHz are measured to be 33-35dB [2].

A CMOS Low-Power Transceiver With Reconfigurable Antenna Interface for Medical Implant Applications

A low-power transceiver for medical implant communication service is presented. The device consists of three subsystems, which perform wake-up signal reception, data-link binary frequency-shift keying (BFSK) reception, and transmission, respectively. A common antenna interface is reused in the three subsystems, reducing circuit complexity and number of external components. Super-regenerative architecture is used for wake-up reception, and gm-boosted common-gate stages are used to optimize receiver (RX) performance with low power consumption. The transmitter employs an all-digital frequency-locked loop to directly drive a class AB power amplifier. The transmitter can alternatively use an injection-locked power oscillator for lower bit rates and power consumption. The integrated circuit is designed and fabricated on a 0.18-μm CMOS process. The wake-up RX achieves a -80-dBm sensitivity for a 50-kb/s signal and a 280-μW dissipation. The BFSK RX achieves a -97-dBm sensitivity for a 75-kb/s signal and a 2-mW power consumption. Finally, the transmitter achieves an output power of -5 dBm for a power consumption of 2.9 mW.

A

Several wireless biomedical transceivers, including medical implants communication systems (MICSs), require ultra-low-power low-complexity frequency synthesizers. This paper presents an all-digital frequency-locked loop (ADFLL)-based frequency synthesizer with a built-in frequency-shift keying modulator for MICS and industrial-scientific-medical band applications. Unlike all-digital phase-locked loops that rely on a power-hungry time to digital converter, the proposed ADFLL employs a high-resolution single-bit ΣΔ frequency discriminator in the feedback path and a noise-cancelling ΣΔ phase-accumulator-based frequency controller in the reference path, achieving fractional resolution with low power consumption. The loop compensation is implemented digitally using an infinite impulse response filter followed by a digital-intensive current-steering DAC driving a ring-oscillator-based voltage-controlled oscillator. The ADFLL achieves 9.5-Hz frequency resolution, spanning the ISM 400-410-MHz band. A worst case near-integer spur of -62 dBc and a phase noise of -83 dBc/Hz at 300-kHz offset are measured. The ADFLL is fabricated on a 0.18-μm CMOS process, occupying a 0.14-mm2 die area, with a quiescent current consumption of 700 μA.

{\hbox{700-}}\mu{\hbox {A}}

A 0.18µm CMOS MICS-band transceiver with a reconfigurable RF front-end is presented, reusing the same circuit core for super-regenerative wake-up receiver, receive-mode LNA, and transmit power amplifier, eliminating the need for an external T/R switch. The transceiver uses an All Digital Frequency Locked-Loop (ADFLL) for LO signal generation and transmitters modulation. The OOK wake-up receiver sensitivity is −80dBm @ 50kbps, while the BFSK receivers sensitivity is −97dBm for a 75kbps signal and 2mW power consumption. The nominal output power of the transmitter is −5dBm.

405-MHz All-Digital Fractional-

An all-digital frequency-locked loop (ADFLL) based frequency synthesizer with a built-in FSK modulator for medical implants communication systems (MICS) band applications is presented. The ADFLL uses a high resolution single-bit digital ΣΔ frequency discriminator in the feedback path and a ΣΔ phase accumulator in the reference path, achieving fractional resolution. The ADFLL uses a digital IIR-based loop filter followed by a digital-intensive ΣΔ current-steering DAC and a first-order-hold filter. The ADFLL achieves 9.5Hz frequency resolution, spanning the ISM 400MHz-410MHz band. The worst-case near-integer spur of −55dBc and a phase noise of −83dBc/Hz at 300kHz offset is measured. The ADFLL is fabricated on a 0.18um CMOS process, occupying 0.14mm2 die area, with a quiescent current consumption of 700uA.

N

This paper illustrates the design of a process compensated bias for asynchronous CML dividers for a low power, high performance LO divide chain operating at 4Ghz of input RF frequency. The divider chain provides division by 4,8,12,16,20, and 24. It provides a differential CML level signal for the in-loop modulated transmitter, and 25% duty cycle non-overlapping rail to rail waveforms for I/Q receiver for driving passive mixer. Asynchronous dividers have been used to realize divide by 3 and 5 with 50% duty cycle, quadrature outputs. All the CML dividers use a process compensated bias to compensate for load resistor variation and tail current variation using dual analog feedback loops. Frabricated in 180nm CMOS technology, the divider chain operate over industrial temperature range (−40 to 90°C), and provide outputs in 138–960Mhz range, consuming 2.2mA from 1.8V regulated supply at the highest output frequency.

Frequency-Locked Loop for ISM Band Applications

A SiGe sub-harmonic down-conversion mixer using a novel active anti-parallel diode pair is presented for millimeter-wave applications. The proposed architecture can help reduce conversion loss and also lower the required local oscillator power. With an LO power of 0 dBm, the measured 2times conversion gain varies from -5 to -7.8 dB in the 50 to 65 GHz range. Compared to earlier reports of millimeter-wave SiGe and GaAs sub-harmonic mixers requiring 5 to 10 dBm of LO power, this circuit achieves similar conversion loss with an LO power as low as -7.5 dBm, while consuming only 0.5 mW of DC power.

A 2mW CMOS MICS-band BFSK transceiver with reconfigurable antenna interface

This brief presents a new design technique for high-efficiency CMOS millimeter-wave power amplifiers (PAs) and the implementations of a two-stage moderate-power PA, a three-stage high-power PA, and a transmitter all working over 68–78 GHz. The proposed PAs adopt nMOS capacitors connected at the gates of the transistors of the last one or two amplifying stages to compensate for the gate capacitance variation over a large signal swing, thus improving the linearity and the power efficiency. Implemented in a 65-nm CMOS process, the two-stage PA achieves a peak power-added efficiency (PAE) of 24.2%, a maximum gain of 17 dB, and a 3-dB bandwidth from 68 to 78 GHz. The three-stage PA achieves a saturated power (Psat) of 17.3 dBm, a peak PAE of 18.9%, and a maximum gain of 21.4 dB. The transmitter consisting of the three-stage PA and a passive double-balanced mixer with local oscillator shaping technique achieves a Psat of 14.6 dBm, a peak efficiency of 13.9%, and a conversion gain of 15.6 dB.

A 700uA, 405MHz fractional-N All digital frequency-locked loop for MICS band applications

This paper presents a low-power 10-Gb/s vertical cavity surface emitting laser (VCSEL) driver integrated circuit (IC) with electrostatic discharge (ESD) protection in the 130-nm CMOS technology. A distributed amplifier (DA)-based modulator is proposed to boost the driver bandwidth. It employs artificial transmission lines to cancel the device parasitic capacitances of the driver. A distributed ESD protection technique is applied to equalize the group delay of the DA to optimize the jitter performance. To minimize the silicon area, the optimal number of DA taps in the proposed modulator has been derived. To compensate for the capacitive load and the channel losses at the output of the driver, a frequency-domain preemphasis scheme is proposed. The proposed DA modulator occupies an area of 0.69 mm2, and the entire driver IC has a die size of 2 mm×2 mm, including the pads. Both electrical and optical tests have been carried out to characterize the performance of the proposed VCSEL driver IC. Measurements at a data rate of 10-Gb/s demonstrate a typical power consumption of 85 mW under a single 2.5 V supply voltage (49 mW, if separate 1.2 and 2.5 V supplies are used) and an rms jitter of 0.63 and 1.12 ps for the electrical test and optical test, respectively.