Paul G. Y. Tsui

Practical applications of 2-D optical proximity corrections for enhanced performance of 0.25 /spl mu/m random logic devices

Simplified 2-D Optical Proximity Correction (OPC) algorithms have been devised, calibrated and implemented on a state-of-the-art 0.25 /spl mu/m random logic process in order to reduce metal line pullback on critical layers. The techniques used are rules-based, but are characterized by fast and robust data conversion algorithms, calibrations based on actual process data, and inspectability of the resultant OPC corrected reticles. Application to local interconnect and metal patterning has corrected fundamental yield-limiting mechanisms in these levels.

Limitation of CMOS supply-voltage scaling by MOSFET threshold-voltage variation

A fundamental limit of CMOS supply-voltage (V/sub CC/) scaling has been investigated and quantified as a function of the statistical variation of MOSFET threshold-voltage (V/sub T/). Based on the data extracted from a sub-0.5 /spl mu/m logic technology, the variation of ring-oscillator propagation-delay (T/sub PD/) significantly increases as V/sub CC/ is scaled down towards the MOSFET V/sub T/ (Fig. 1). An empirical power-law relationship was then derived to describe the scattering of circuit speed (/spl Delta/T/sub PD/) as a function of MOSFET V/sub T/ variation(/spl Delta/V/sub T/) and (V/sub CC/-V/sub T/). Agreement between the model and the experimental data was established for V/sub CC/ values from 4.0 V to 0.9 V. This fundamental limit of CMOS V/sub CC/ scaling poses an additional challenge for the design and manufacturing of high-performance, low-power portable equipment and battery based systems.<<ETX>>

A fully complementary BiCMOS technology for sub-half-micrometer microprocessor applications

A modular process architecture has been adopted to develop a versatile yet manufacturable, single-poly, four-level metal, fully complementary BiCMOS technology for sub-0.5- mu m microprocessor products. Both the poly-emitter vertical n-p-n and p-n-p bipolar transistors are integrated into a dual-poly (n/sup +//p/sup +/) gate CMOS process flow. Using a collector pedestal implant in the emitter window, the n-p-n performance has been enhanced to 26 GHz. Lateral p-n-p and TiSi/sub 2/ Schottky-barrier diode are also available for circuit applications. Stacking of the tungsten-plug contacts and vias are allowed in the multilevel metallization module. Comparing the CMOS and BiCMOS implementation of a 68030 critical path, 40% speed improvement at 3.3-V Vcc and a CMOS/BiCMOS crossover at 2.2 V have been obtained for this logic BiCMOS technology. >

A 0.4 micron fully complementary BiCMOS technology for advanced logic and microprocessor applications

A modular process architecture has been adopted to develop a versatile yet manufacturable, single-poly, four-level metal, fully complementary BiCMOS technology for sub-0.5 mu m logic and microprocessor products. Both the poly-emitter vertical n-p-n and p-n-p bipolar transistors are integrated into a dual-poly (n/sup +//p/sup +/) gate CMOS process flow. Using a pedestal implant in the emitter window, the n-p-n performance has been enhanced to 26 GHz. Lateral p-n-p and TiSi/sub 2/ Schottky barrier diode devices formed during the titanium self-aligned silicide process are available for various circuit applications. Stacking of the tungsten-plug contacts and vias is allowed in the multilevel metallization module. A process window analysis has also been performed to derive the optimal device design targets. Compared with the CMOS counterpart, approximately 40% speed improvement (at 3.3 V V/sub cc/) in a 68030 critical path has been demonstrated using this logic BiCMOS technology.<<ETX>>

Suppression of MOSFET reverse short channel effect by N/sub 2/O gate poly reoxidation process

We show that an N/sub 2/O oxynitride post-gate poly reoxidation process is effective in suppressing the reverse short channel effect (RSCE). A significant reduction in RSCE (/spl sim/30%) was obtained experimentally for the N/sub 2/O reoxidation process compared to the standard O/sub 2/ thermal reoxidation. A reduced level of interstitial injection by the oxynitridation of silicon interface is believed to be responsible for counteracting the local oxidation enhanced lateral diffusion. We further identify the critical trade-offs in channel profile engineering. That is, transistors with high channel mobility suffers from more pronounced RSCE if subject to interstitial injection after the gate definition. Excellent sub-half micron CMOS device and low-voltage ring oscillator performance are demonstrated using this process.<<ETX>>

Study of BiCMOS logic gate configurations for improved low-voltage performance

A simple BiCMOS configuration employing the source-well tie PMOS/n-p-n pull-down combination is proposed for low-voltage, high-performance operations. The improved BiCMOS gate delay time over that of the NMOS/n-p-n (conventional) BiCMOS gate is confirmed by means of inverter simulations and measured ring oscillator data. The source-well tie PMOS/n-p-n BiCMOS gate outperforms its conventional BiCMOS counterpart in the low-voltage supply range, at both high and low temperatures. A critical speed path from the 68030 internal circuit is used as a benchmark for the proposed BiCMOS design technique. The measured propagation delay of the BiCMOS speed path is faster than its CMOS counterpart down to 2.3 V supply voltage at -10 degrees C and sub-2 V at 110 degrees C. >

A circuit level hot-carrier evaluation system

A fully integrated system that facilitates the evaluation and prediction of hot-carrier effects at the circuit level is described. The system is capable of executing constant voltage and constant current ratio stress conditions at the transistor level, performing extensive data analysis and extraction, and simulating circuit reliability at a user-defined future time. Through these enhancements, more precise model parameter values can be attained, which in turn improves the overall accuracy of the circuit aging simulation. Quantitative verification of the simulation results against experimental data was accomplished using 0.5- mu m CMOS ring oscillators. The reliability of the ring oscillators as a function of stress time, power supply voltage, capacitive loading, and passivation technology is analyzed. In all these cases, less than 2% absolute error was observed between the experimental and simulation results when using this automated hot-carrier evaluation system. >

Field-plated high gain lateral bipolar transistor in standard CMOS process for BiNMOS application

A high-gain gate-assisted lateral bipolar n-p-n transistor with current gain of over 3000 was fabricated in a compatible p-well CMOS process. The device was fabricated using the same mask sequences as that of an n-channel MOSFET with its gate connected to the p-well. With the assistance of the PISCES device simulator, total collector current was found to have two main components, the gale-assisted component and the bulk bipolar component. A circuit model with parallel MOSFET and bipolar transistors was used to verify DC measurement results.<<ETX>>

An integrated system for circuit level hot-carrier evaluation

An integrated system designed to evaluate and predict hot-carrier effects at the circuit level is described. The system will perform device stress, collect data, extract parameters, and simulate circuit aging behavior using the circuit aging simulator from UC Berkeley. Enhancements made to the device-stress and data-analysis portions of the system were found necessary to achieve accurate circuit reliability prediction. Less than 2% error is observed between the measured and simulated performance of a 0.5 mu m ring oscillator test circuit.<<ETX>>

0.25-μm logic manufacturability using practical 2D optical proximity correction

Simplified 2-D Optical Proximity Correction (OPC) algorithms have been devised, calibrated and implemented on a state-of- the-art 0.25 micrometer random logic process in order to reduce metal line pullback on critical layers. The techniques used are rules-based, but are characterized by fast and robust data conversion algorithms, calibrations based on actual process data improvements in reticle manufacturability, and inspectability of the resultant OPC corrected reticles. Application to local interconnect and metal patterning has corrected fundamental yield-limiting mechanisms in these levels.