Matthew A. Thompson

Reticle enhancement technology: implications and challenges for physical design

In this paper, we review phase shift lithography, rule vs. model based methods for OPC and model-based tiling, and discuss their implications for layout and verification. We will discuss novel approaches, using polarizing films on reticles, which change the game for phase-shift coloring, and could lead to a new direction in c:PSM constraints on physical design. We emphasize the need to do tiling that is model-driven and uses optimization techniques to achieve planarity for better manufacturing tolerance in the subwavelength dimensions era. Electromagnetic solver results will be presented which estimate the effect of tiling on circuit timing.

Extreme ultraviolet lithography mask patterning and printability studies with a Ta-based absorber

Extreme ultraviolet (EUV) lithography masks were fabricated using a stack of TaSi or TaSiN (absorber), SiON (repair buffer), and Cr (conductive etch stop) on a Mo/Si multilayer mirror deposited on a Si wafer. High-resolution structures were exposed using a commercial i-line resist, and the pattern was transferred using both electron cyclotron resonance and reactive ion etching with halogen-based gases. Process temperatures to fabricate these reticles were always maintained below 150 °C. EUV properties after patterning were measured using a synchrotron source reflectometer. Completed masks exhibited a negligible shift in the peak wavelength and less than 2% loss in reflectivity due to processing. Qualified masks were exposed with a 10× EUV exposure system. The exposures were made in 80-nm-thick DUV resist and with numerical apertures (NA) of 0.08, 0.088, and 0.1. Resolution down to 70 nm equal lines and spaces was achieved at a NA of 0.1. Line edge roughness in the resist features was 5.5 nm (3σ, one side)...

Extendibility of x‐ray lithography to ⩽130 nm ground rules in complex integrated circuit patterns

Previous experimental and theoretical evidence indicates that x‐ray lithography can be used to pattern ≤180 nm features. In order to be used in manufacturing, x‐ray lithography of complex integrated circuit patterns (i.e., dense two‐dimensional patterns) needs to be demonstrated with a practical proximity gap. However, no large body of experimental evidence exists for the extendibility of x‐ray lithography for complex patterns with ground rules of ≤130 nm at gaps of 10–20 μm. Simulations of image formation and resist dissolution are shown to have good agreement with experimental results. These simulations are then used to predict exposure latitude and gap latitude for printing one‐dimensional 75–125 nm patterns at 10–15 μm gaps. Simulations indicate that at least ±10% exposure dose latitude will exist for simple patterns at these gaps, but significant nested‐to‐isolated linewidth bias will exist. Gaps must be controlled to ±1 μm for ±10% dose latitude. More complex two‐dimensional patterns have been shown...

Overlay measurement and analysis of x-ray/optical lithography for mix-and-match device applications

A joint Motorola/IBM experiment was performed in mix-and-match lithography across widely separated locations. A simple pattern placement metrology data set was created, and x-ray masks were manufactured according to this data. The same data was converted into a 5x reticle and optically stepped on wafers. The x-ray mask was designed to print upon two optical fields with one x-ray exposure. The x-ray mask was aligned to the wafers to produce box-in- box images for overlay metrology. The main overlay problems encountered were systematic offsets between x-ray and optical images, and average magnification error of approximately 8 ppm. The magnification error is substantial because of the 3 degree(s)C temperature difference between the optical stepper stage and the x-ray mask-writer. In an actual device run, the magnification differences will be removed by compensation in the e-beam writing of the x-ray mask. Offsets will be removed by use of a send-ahead wafer to determine the correct offset alignment in the x-ray stepper.

Effects of complementary phase-shift imaging on gate CD control

Gate patterning has always been held to tight specifications for CD variation compared to other layers. Specifically, the gate layer is more concerned with the total CD variations including Across Chip Linewidth Variation (ACLV), Across Wafer Linewidth Variation (AWLV), CD variation through pitch (Proximity bias), than other layers. Therefore, complementary phase shift (c:PSM) imaging has been introduced at the gate layer under the assumption that it will reduce the total CD variation compared to binary imaging. However, c:PSM data conversion of random logic can introduce additional biases that also impact CD control. These new biases include CD variation as a function of shadow size, reticle-to-reticle overlay error, shifter width, and shifter height (a function of the transistor width and the shifter extension). This paper will show the improvements in ACLV and AWLV using c:PSM. This paper will also look at the increase in the proximity bias for c:PSM compared to binary imaging and show results for implementing a 1-D OPC correction on the phase shift reticle. In addition, this paper will also look at the magnitude of the various additional c:PSM biases mentioned. This paper will discuss the interaction of the different phase shift conversion input parameters for complex random logic and the limitations they impose on how tight we can make the final CD distribution. Finally, since c:PSM allows for selective sizing of CDs over active and over field, a brief discussion will also be given for the CD control of the complementary binary reticle.

Electrical linewidth measurements and simulations studying the effects of dose and gap on exposure latitude in x-ray lithography

Electrical linewidth measurements of etched, N+-doped polysilicon submicron lines were carried out to study the effects of dose and gap on exposure latitude in proximity X-ray lithography. Isolated lines and equal line/space pairs having linewidths from 0.15 micrometers to 0.35 micrometers on the X-ray mask were printed in APEX-M resist at gaps ranging from 26 micrometers to 34 micrometers using a Karl Suss stepper. Lithography was carried out at the IBM Advanced Lithography Facility using the Helios 1 synchrotron. Low voltage scanning electron microscopy (SEM) measurements in top-down mode using the linear regression algorithm are compared to electrical linewidth measurements. Reactive-Ion Etch bias is determined by comparing top-down SEM of resist after exposure, on both 50 and 330-nm-thick polysilicon, to top-down SEM after etching. Both resist and etched line profiles are examined in cross section using SEM. The etch bias and the change in line profiles were found to account for most of the offset between the SEM and the electrical linewidth measurements. The results of SEM-measured averaged across the field, were also compared to two-dimensional aerial images (determined using average SEM-measured mask linewidths) and resist dissolution simulations to examine simulation accuracy.

Practical quality metrics for resolution enhancement software

The past few years have seen an explosion in the application of software techniques to improve lithographic printing. Techniques such as optical proximity correction (OPC) and phase shift masks (PSM) increase resolution and CD control by distorting the mask pattern data from the original designed pattern. These software techniques are becoming increasingly complicated and non-intuitive; and the rate of complexity increase appears to be accelerating [1]. The benefits of these techniques to improve CD control and lower cost of ownership (COO) is balanced against the effort required to implement them and the additional problems they create. One severe problem for users of immature and complex software tools and methodologies is quality control, [2] as it ultimately becomes a COO problem. Software quality can be defined very simply as the ability of an application to meet detailed customer requirements. Software quality practice can be defined as the adherence to proven methods for planning, developing, testing and maintaining software. Although software quality for lithographic resolution enhancement is extremely important, the understanding and recognition of good software development practices among lithographers is generally poor. We therefore start by reviewing the essential terms and concepts of software quality that impact lithography and COO. We then propose methods by which semiconductor process and design engineers can estimate and compare the quality of the software tools and vendors they are evaluating or using. We include examples from advanced process technology resolution enhancement work that highlight the need for high-quality software practices, and show how to avoid many problems. Note that, although several authors have worked in software application development, our analysis here is somewhat of a black box analysis. The black box is the software development organization of an RET software supplier. Our access to actual developers within these organizations is very limited. In so far as our comments with respect to the internal workings of these development organizations go, we rely on the interactions we have had with applications engineers and other technical specialists who provide our interface to the development organizations.

Model-based design improvements for the 100-nm lithography generation

Due to the challenging design rule and CD control requirements of the 100 nm device generation, a large number of complex patterning techniques are likely to be used for random logic devices. The complexity of these techniques places considerable strain upon model-based OPC software to identify and compensate for a wide range of printing non- idealities. Additionally, the rapidly increasing cost of advanced reticles has increased the urgency of obtaining reticles devoid of process limiting design or OPC errors. We have evaluated the capability of leading edge model-based OPC software to meet the challenging lithography needs of the 100 nm device generation. Specifically, we have implemented and verified model usefulness to correct for pattern deformation in complex binary gate, contact and via processes utilizing highly optimized illumination. Additionally, we present results showing the abilities of model-based methods to accurately find design related printing problems in complementary phase shift gate designs before they are committed to an expensive reticle.

High-performance 0.25-um CMOS technology for fast SRAMs

A high performance 0.25 micrometers CMOS process has been developed for fast static RAMs. This technology features retrograde wells, shallow trench isolation scalable to a 0.45 micrometers active pitch, surface channel 0.25 micrometers NMOS and PMOS transistors with a 55 angstroms nitrided gate oxide providing drive currents of 630 and 300 (mu) A/micrometers respectively at off-leakages of 10 pA/micrometers , overgated TFTs with an on/off ratio greater than 6(DOT)105, stacked capacitors for improved SER protection, five levels of polysilicon planarized by chemical-mechanical polishing with two self-aligned interpoly contacts, 0.35 micrometers contacts and a 0.625 metal pitch. In this technology, a triple well structure was used for SER protection. High energy retrograde wells were integrated with shallow trench isolation and epi providing excellent interwell isolation for both leakage and latch-up down to n+/p+ spaces of 0.60 micrometers . PMOS transistors were scaled to a physical gate length of 0.1 micrometers while maintaining excellent short channel characteristics. A split word-line bitcell was scaled to 1.425 micrometers X 2.625 micrometers equals 3.74 micrometers 2 using 0.25 micrometers rules. A tungsten interpoly plug was used to connect the PMOS TFT loads to the underlying NMOS latch gates without a parasitic diode or dopant interdiffusion, connecting 3 polysilicon layers with self-aligned isolation from an intervening polysilicon layer used as a local interconnect. With this plug, TFT drive currents were greatly improved, particularly at low voltages and the memory nodes pulled to the fully supply voltage. Functional 0.25 micrometers bitcells were demonstrated and with an LDD resistor it was possible to double the cell stability. Bitcell simulation was used to demonstrate that a 4T bitcell will be stable at 2.5 V but that a word-line boost will be required for 1.8 V operation.

Trench isolation at 300 nm active pitch using x‐ray lithography

A nanofabrication technology providing device isolation at an active pitch of 300 nm has been developed using x‐ray lithography for pattern definition. The isolation scheme uses oxide filled trenches etched into the silicon substrate, which are 300–350 nm deep and have a 150 nm minimum width. Chemical mechanical polishing is utilized to achieve global planarization. The superior diode leakage and gate oxide (tox=55 A) performance, excellent metal–oxide–semiconductor field effect transistor characteristics, and robust latch‐up behavior demonstrated by this trench isolation technology, present it as a key enabler for continued scaling of semiconductor technologies. The experimental data presented predicts that with careful attention to process integration, trench isolation can be scaled well into the sub‐0.25 μm size scale.