Petar Biljanović

Fabrication of horizontal current bipolar transistor (HCBT)

The fabrication and characterization of very compact horizontal current bipolar transistor (HCBT) is presented. The active transistor region is processed in the sidewalls of the n-hill, which makes this structure attractive for the integration with pillar-like CMOS with minimum process additions. HCBT technology is simple with 5 lithography masks. The active n-hills are isolated by newly developed chemical-mechanical planarization (CMP) and etch back of oxide. The substrate is used for HCBT fabrication utilizing crystal planes as the active sidewalls. This enables the use of crystallographic dependent etchants for the minimization of the sidewall roughness and dry etching defects, as well as increases the controllability and repeatability of intrinsic transistor doping process. The active transistor regions are processed by angled ion implantation in self-aligned manner. The processed structures result in a cutoff frequency-breakdown voltage (f/sub T/BV/sub CEO/) product of 69.5 GHzV and current gain-Early voltage (/spl beta/V/sub A/) of 4800 V. The high-frequency characteristics are limited by the wide extrinsic base due to the coarse lithography resolution used for fabrication. It is shown by simulations that the improvement of (f/sub T/) and maximum oscillation frequency (f/sub max/) up to 24 and 50 GHz, respectively, can be achieved with finer lithography employed.

Horizontal current bipolar transistor (HCBT): a new concept of silicon bipolar transistor technology

A new concept of silicon bipolar transistor technology is proposed. The resulting horizontal current bipolar transistor (HCBT) is simulated assuming the 0.25 /spl mu/m technology. The surface of the device is smaller than conventional super-self aligned bipolar transistors. The same doping profile as in known vertical current devices is achieved by simpler technology using single polysilicon layer, without conventional epitaxial and n/sup +/ buried layers and with reduced number of lithography masks and technological steps. The simulated dc and ac characteristics of HCBT are similar to the characteristics of standard SST devices.

A new HCBT with a partially etched collector

A novel horizontal current bipolar transistor (HCBT), suitable for the integration with the pillar-like MOSFETs, is processed with the reduced volume of the parasitic regions, achieved by the partial etching of the collector n-hill region and the self-protection of the p/sup +/ extrinsic base from tetramethyl ammonium hydroxide etch-back. The HCBT fabricated by a low-cost technology exhibits the cutoff frequency (f/sub T/) of 30.4 GHz, the maximum frequency of oscillations (f/sub max/) of 35GHz and the collector-emitter breakdown voltage (BV/sub CEO/) of 4.2 V, which are the highest f/sub T/ and the highest f/sub T/BV/sub CEO/ product among the lateral bipolar transistors (LBTs).

A novel low-cost horizontal current bipolar transistor (HCBT) with the reduced parasitics

A novel horizontal current bipolar transistor (HCBT) structure, suitable for the integration with pillar-like MOSFETs, is presented. The HCBT is processed by a low-cost technology in the (111) sidewalls on the [110] wafers, with minimized volume of the extrinsic regions, resulting in reduced parasitics. The HCBT structure exhibits the highest f/sub /spl tau// (30.4 GHz) and f/sub T/BV/sub CEO/ product (127.7 GHzV) among the lateral bipolar transistors.

Minimization of sidewall roughness in Si pillar-like structures by photolithography optimization

The sidewall roughness of silicon pillar-like structures degrades the characteristics of both optical MEMS and MOS or bipolar electron device applications. The silicon pillar sidewall roughness comes from the photoresist edge roughness caused by the polymer chains entangled in aggregates, which has a higher density than the surrounding polymer and hence the lower development rate. Therefore, the photolithography optimization of AZ 5214 photoresist is carried out in order to achieve minimal sidewall roughness. The steps that influence the roughness most are: sample preparation and handling procedures, photoresist thickness, hardbake temperature and O/sub 2/ plasma descum. The silicon sample is cleaned and handled in a way to minimize the particle contamination on the surface since exposure is done in contact mode and any kind of particles would increase the gap between the mask and sample causing a lateral distribution under the mask patterns due to the diffraction effect. Photoresist is spun on the sample to achieve smaller thickness to minimize the light diffraction inside the photoresist. During hardbake, photoresist reflows and the edge roughness is reduced. The optimum temperature is 150/spl deg/C. By applying O/sub 2/ plasma descum, the edge roughness is reduced due to the isotropic nature of the process.

Thermionic emission process in carrier transport in pn homojunctions

Thermionic emission is treated in pn homojunctions. Thermionic current over pn junction barrier is derived directly from Maxwell-Boltzmann distribution function as a difference between the majority carrier flow and the flow of excess carriers in the opposite direction. It is shown that the excess carrier concentration is determined as an equilibrium between thermionic and diffusion process, which depends on quasi-neutral region width. Total current is limited by thermionic process for very thin quasi-neutral regions. Such an approach enables the determination of boundary condition for any doping profile.

High-frequency analysis of SOI lateral bipolar transistor (LBT) structure for RF analog applications

The Lateral Bipolar Transistor (LBT) on SOI substrate for RF analog applications with extrinsic base on the top of the collector n-region is analyzed. The extrinsic base affects f/sub T/ and f/sub max/ in several ways. First, it increases C/sub BC/ making it dependent on lithography resolution. Second, depending on collector-base voltage, a collector-base depletion region decreases the effective collector cross-section area thus causing the Kirk effect to occur at lower collector currents. Third, the electrons injected from emitter flow partly through the extrinsic base-collector depletion region increasing the effective transit time. With respect to those effects, the technological parameters are varied and the impact on f/sub T/ and f/sub max/ are analyzed. It is shown that the increase of f/sub T/ can be achieved without sacrificing f/sub max/ considerably only by changing device geometry, still using the same doping profile of the intrinsic transistor region.

Low temperature resistivity of heavily boron doped LPVCD polysilicon thin films

Heavily boron δ-doped polysilicon samples were prepared by horizontal low-pressure chemical vapour deposition (LPCVD) at 750 ◦ C for 1h and were annealed at 1200 ◦ C for 1h. In this way, the samples with low sheet resistance down to 8.9 � sq −1 , were obtained. The boron concentration was determined from the room temperature sheet resistance. The resistivity was measured from room temperatures down to 2K. A T 1/2 dependence of the conductivity in an unusually wide temperature interval, even up to 80K was observed. Above 140K, the resistivity can be described by the T 3/2 dependence. The experimental results were analysed within the theories for the disordered metals and compared with the corresponding existing resistivity data.

Raman scattering technique in characterisation of glasses containing silicon nanoparticles for optoelectronics

The Raman scattering on acoustical phonons from silicon quantum dots in glass matrix were investigated. Two peaks that correspond symmetric and quadrupolar modes of spherical vibrations were found and compared with the model calculation for in- and off-resonance scattering conditions. In both models the homogeneous broadening due to interaction with matrix and inhomogeneous broadening due to particle size distribution as well as the frequency red shift were found. The comparison of the model fit on the Raman spectra with the size distributions measured by HRTEM showed that resonant scattering mechanism with the light to vibration coupling coefficient strongly dependent on the particles size is responsible for the observed Raman spectra.

A BV/sub CEO/ engineering in horizontal current bipolar transistor (HCBT) technology

A need for different breakdown voltages of vertical-current bipolar transistors on the same chip is accomplished by added process complexity and increased fabrication costs. In horizontal current bipolar transistor (HCBT) technology, the devices with different collector-emitter breakdown voltages (BVCEO) can be fabricated just by changing the mask dimensions, without any addition to process flow. Extrinsic base has a main effect on BVCEO due to charge sharing effect. Cutoff frequency and maximum frequency of oscillations of HCBT structures with different extrinsic base widths are measured together with BVCEO. The optimum fTBVCEO product of more than 100 GHzV is achieved at extrinsic base width of 0.8 mum. The charge sharing effect is analyzed by 2D simulations and the reduction of the peak electric field in the intrinsic region is shown. Moreover, the increase of BVCEO at low base currents is measured and explained by the current gain reduction due to SHR recombination in emitter-base depletion region. The breakdown occurs in different regions of HCBT structure at low and high currents