Peter A. Gruber

Low-cost wafer bumping

As the demand for flip-chip interconnects mounts across an increasingly large spectrum of products and technologies, several wafer-bumping proeesses have been developed to produce the small solder features required for this interconnect technology. These processes differ signicantly in complexity and commensurate cost. Recently, a new bumping process developed at IBM Research called injection-molded solder, or IMS, has shown the capability to combine low-cost attributes with high-end capabilities. The development of IMS technology was driven by the need to reduce wafer-bumping costs while simultaneously addressing the conflicting needs of increasing wafer dimensions to 300 mm, decreasing bump and pitch dimensions below 75 µm on 150-µm centers, and optimal Pb-free alloy selection and processing. This paper describes IMS technology for both standard eutectic SnPb and Pb-free wafer bumping. Existing mainstream bumping technologies are also reviewed, with a focus on the challenges of new industry requirements. Early manufacturing challenges are addressed, including solutions that demonstrated the appropriateness of IMS technology for low-cost 300-mm Pb and Pb-free wafer bumping. Early process and reliability data are also reviewed.

Pb-free solder alloys for flip chip applications

In addition to the environmental issue regarding the use of Pb-bearing solders in microelectronics applications, there is another issue associated with using Pb-bearing solders in interconnections, like flip chip solder interconnections in an advanced CMOS technology, that are near active circuits. In order to minimize the soft error rate due to alpha particle emission from Pb-bearing solder alloys, Pb-free solder alloys were studied as possible replacements for the Pb-based solders that are presently used in flip chip interconnections. A large number of solder compositions was selected for evaluation. Since all the candidate alloys were Sn-based, alternatives for the ball-limiting metallurgy (BLM) were also investigated. The physical, chemical, mechanical and electrical properties of the alloys were determined by thermal analysis, wettability testing, microhardness measurement, electrical resistivity measurement, interfacial reaction study and others. Test vehicles were also built with some selected Pb-free solder alloys with the proper BLM to evaluate integrity of the flip chip solder bump structure. Based on this study, a few candidate solder alloys were selected with a proper BLM barrier layer for flip chip applications.

Injection molded solder technology for Pb-free wafer bumping

A new wafer bumping technology is described that is especially suited for Pb-free applications. Although capable of using standard PbSn eutectic solder, IMS (injection molded solder) has been found to be especially suited for accommodating a wide range of Pb-free alloys with equal ease. The development of IMS technology was driven by the need to reduce wafer bumping costs while simultaneously addressing the conflicting demands of increasing wafer dimensions to 300 mm and decreasing bump and pitch dimensions below 75 /spl mu/m on 150 /spl mu/m centers. The IMS wafer bumping process uses a new head assembly that melts bulk solder alloys with precisely controlled compositions and dispenses the molten solder into multiple cavities of a wafer-sized mold plate. The mold plate is CTE matched to silicon and is reusable many times, thus reducing the per wafer bumping cost. In the process, a mold plate is scanned and filled with molten solder and inspected after solidification. Thereafter, the mold plate and device wafer are aligned and adjoined in a mirror image fashion for processing through a solder reflow furnace to transfer solder to the wafer. In this paper, early manufacturing challenges and solutions are described which allow IMS to be considered as an attractive technology for 300 mm Pb-free wafer bumping. Early process feasibility data for 200 mm wafer bumping are reviewed. Economical and environmental advantages are also discussed in relation to key process characteristics, such as solder waste reduction, use of low-cost bulk alloys, and others.

50μm pitch Pb-free micro-bumps by C4NP technology

Controlled collapse chip connection new process (C4NP) is currently used in IBM manufacturing for all 300 mm Pb-free wafer bumping for flip chip packages. In this study, the extendibility of C4NP technology to ultra fine pitch applications has been explored. Reusable C4NP glass molds were fabricated and characterized for 50 mum pitch application. Mold fill and wafer transfer with Pb-free solders have been demonstrated using both 200 mm and 300 mm wafers in a manufacturing environment. Significant improvement in bump yield was achieved for these early demonstrations of fine pitch interconnections through process optimization and contamination control. Challenge in wafer inspection metrology is discussed for the 50 mum pitch micro-bumps. Mechanical strength of the C4NP micro-bumps has been characterized using test dies with a full area array of micro-bumps.

Injection molded solder - A new fine pitch substrate bumping method

Injection molded soldering (IMS) technology has been developed for solder bumping of fine-pitch organic substrates. Pure molten solder is injected through a flexible film mask that is aligned to the recessed pad openings to form solder bumps on the substrate. The new substrate bumping method is a simple one pass operation for various size pads, with the capability of forming high solder volume on fine pitch substrate.

C4NP Lead Free Solder Bumping and 3D Micro Bumping

Semiconductor packaging continues to migrate from wire bond to flip chip first level interconnect to meet aggressive size, weight and electrical performance requirements. In addition, novel System in Package (SiP) approaches utilizing 3D packaging technologies and fine-pitch chip to chip interconnection schemes require advanced lead-free solder bumping technologies. Today, solder electroplating is commonly employed for wafer bumping, especially for fine pitch applications. Wafer level chip scale packaging (WLCSP) typically utilizes solder sphere placement technology to manufacture the bumps. C4NP (Controlled Collapse Chip Connection New Process) has proven to be suitable for a broad range of solder bump pitches, from 3D FC to CSP bump dimensions. As the industry migrates to 300 mm wafer processing and lead-free flip chip intercon nect, C4NP is establishing itself as a viable solder bumping alternative. IBM is ramping production in C4NP and shipping bumped lead-free 300 mm wafers. This paper reviews the C4NP process from mold manufacturing to lead free solder transfer onto 300 mm wafers. Technology applications are summarized, including C4 interconnects and three dimensional (3D) integration. This paper reviews C4NP micro bumping results in support of 3D packaging, and early manufacturing yield results from 300 mm wafer development and manufacturing. Lastly, the most recent lead-free reliability data for both 200mum & 150mum C4 pitch for plated BLMstructures is summarized.

C4NP for Pb-free solder wafer bumping and 3D fine-pitch applications

Controlled collapse chip connection - new process (C4NP) technology is a novel solder bumping technology developed by IBM to address the limitations of existing bumping technologies. Through continuous improvements in processes, materials and defect control, C4NP technology has been successfully implemented at IBM in the manufacturing of all 300 mm Pb-free solder bumped wafers. Both 200 mum and 150 mum pitch products have been qualified and are currently ramping up volume production. Extendibility of C4NP to 50 mum ultra-fine pitch microbump application has been successfully demonstrated with the existing C4NP manufacturing tools. Targeted applications for microbumps are three-dimensional (3D) chip integration and the conversion of memory wafers from wirebonding (WB) to C4 bumping. The metrology data on solder volume, bump height, defect and yield have been characterized by RVSI inspection. This paper reviews the C4NP processes from mold manufacturing, solder fill and solder transfer onto 300 mm wafers, along with defect and yield analysis. Reliability challenges as well as solutions in the development and qualification of flip chip Pb-free solder joint are also reviewed. In addition to a suitable under bump metallurgy (UBM), a robust lead-free solder alloy with precisely controlled composition and special alloy doping is needed to enhance performance and reliability.

C4NP - IBM Manufacturing & Reliability Data for Lead Free Flip Chip Solder Bumping

C4NP (C4-New Process) is a novel solder bumping technology developed by IBM and commercialized by Suss MicroTec. C4NP addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping using a variety of lead-free solder alloys. C4NP is a solder transfer technology where molten solder is injected into pre-fabricated and reusable glass templates (molds). The filled mold is inspected prior to solder transfer to the wafer to ensure high final yields. The filled mold and wafer are brought into close proximity and solder bumps are transferred onto the entire 300 mm (or smaller) wafer in a single process step without the complexities associated with liquid flux

C4NP Cu-cored Pb-free flip chip interconnections

We report here preliminary results on a new Cu-cored flip chip structure combining C4NP (Controlled Collapse Chip Connect New Process) with Cu spheres for high density interconnections. C4NP is a new wafer bumping technology developed by IBM in which molten solder is injected into a mold and then transferred to the UBM (Under Bump Metallurgy) pads on the wafer. This simple and parallel process has shown the capability to combine low cost attributes with high performance capabilities. C4NP allows a larger number of interconnections with finer pitch than screen printing methods because it eliminates the volume reduction problem of solder paste. Also, C4NP allows more freedom in selecting the composition of solder bumps when compared with the electroplating method. To make Cu-cored flip chip interconnections with C4NP, Cu spheres are arrayed in the cavities on a mold which matches the CTE of the wafer. The Cu spheres are then transferred from the Si mold to C4NP solder bumps on the wafer by using the same process used for C4NP solder transfer. Then, after dicing, the diced chip is flip chip assembled on the substrate which has been pre-soldered. This combination of C4NP and Cu spheres is a dry process with potential for low cost, because it does not need thick photoresist, lithography, or plating process steps. Our early laboratory demonstrations of Cu-cored bumping have processed individual chips rather than full wafers; but, based on our manufacturing experience with C4NP solder bumping, we expect the process to be readily extendible to wafer scale. The C4NP Cu-cored flip chip joints offer potential advantages in stress mitigation and electrical performance. The centered Cu sphere in the joint ensures greater stand-off for fine pitch, which facilitates the underfill process and improves fatigue resistance due to the taller bump. The low electrical resistivity of Cu enhances current carrying capacity. The small Sn/Cu ratio in the bump would decrease UBM consumption and solder depletion under high current stressing. The high thermal conductivity of Cu also enhances heat transfer from the chip to the substrate. Due to the high Cu/Sn ratio in the flip chip interconnections, the higher Youngs modulus of Cu over solder could be a concern for stress concentration on the IC despite the higher stand-off height provided by the Cu-core bump. However, in the C4NP Cu-cored flip chip structure, since the transfer mold is used for inserting Cu spheres into the flip chip joints, Cu spheres can be selectively deployed only to the joints where the composite bumps are required, whereas the other, highly stressed joints can be electrically connected without Cu spheres. Therefore, the selective use of composite interconnects may allow stress to be minimized while optimizing electrical performance.