Peter Alpern

A Temperature-Gradient-Induced Failure Mechanism in Metallization Under Fast Thermal Cycling

In this paper, a novel mechanism is shown to cause the failure evolution in a metallization system under fast temperature cycle stress. The failure evolution is triggered by the lateral temperature distribution across the device, which causes an accumulating plastic deformation of the metallization. The root cause for the deformation emerges at the position of the maximum gradient in temperature.

Investigation and Improvement of Fast Temperature-Cycle Reliability for DMOS-Related Conductor Path Design

During operation double-diffused-MOS (DMOS) transistors are subjected cyclically to severe temperature pulses. The resultant thermo-mechanical stress causes a viscoplastic deformation of the metallization. This increases the local stress on the interlayer dielectric (ILD) beyond a critical limit and results in ILD cracking. The DMOS fails due to electric short-circuits, that are caused by extruding aluminum. Due to its relevance for the DMOS design, the influence of the conductor line width is studied with a special test structure (Nguyen et al., 2002). From the observed failure evolution an effective method to improve fast temperature-cycle reliability is derived.

On the Way to Zero Defect of Plastic-Encapsulated Electronic Power Devices—Part I: Metallization

Concerning thermomechanically induced failures, such as metal line deformation and passivation cracks, there is a practicable way to achieve the zero-defect limit of plastic-encapsulated power devices. This limit can be reached by evaluating the influence of the major components involved and, consequently, by selecting the appropriate materials and measures. On the other hand, the interdependence between all components must always be kept in mind, i.e., chip and package have to be regarded as an entity. An important finding was that applying simply one improvement step will not necessarily lead to the desired goal. Only the implementation of all improvement steps considering their interdependence is the key for the perfect overall system chip and package. In Part I of this series of papers, the yield stress of the power metallization is shown to play a crucial role for the generation of metal deformation and passivation cracks. Understanding the ratcheting mechanism led to the development of a new layered metallization material with a distinctly increased yield stress, resulting in a considerably reduced failure generation.

On the Way to Zero Defect of Plastic-Encapsulated Electronic Power Devices—Part II: Molding Compound

Concerning thermomechanically induced failures, such as metal line deformation and passivation cracks, there is a practicable way to achieve the zero-defect limit of plastic-encapsulated power devices. This limit can be reached by evaluating the influence of the major components involved and, consequently, by selecting the appropriate materials and measures. On the other hand, the interdependence between all components must always be kept in mind, i.e., chip and package have to be regarded as an entity. An important finding was that applying simply one improvement step will not necessarily lead to the desired goal. Only the implementation of all improvement steps considering their interdependence is the key for the perfect overall system chip and package. In Part II of this series of papers, the thermomechanical influence of the molding compound (MC) on the chip, i.e., the root cause of metal deformation and passivation cracks, was studied in great detail. Concerning the generation of these failures, the coefficient of thermal expansion was shown to play a key role. However, for a full understanding of the thermomechanically induced damage, the viscoelastic properties of the MC have to be considered.

A simple model for the mode I popcorn effect for IC packages

Abstract A simple model for the Mode I popcorn effect is presented here for packages with rectangular die pad (P-DSO). A package “stability parameter”, relating to its moisture sensitivity, is derived from the popcorn model. It describes the critical factors for a robust package - molding compound properties and package, leadframe design for a given preconditioning and soldering process. Furthermore, nomograms generated from the model enable an easy estimation of moisture sensitivity levels (between 1 and 5) of packages with different die pad sizes and molding compound underpad thicknesses and for different soldering temperatures ranging from 220°C to 260°C (Pb-free soldering).

On the Way to Zero Defect of Plastic-Encapsulated Electronic Power Devices—Part III: Chip Coating, Passivation, and Design

Concerning thermomechanically induced failures such as metal-line deformation and passivation cracks, there is a practicable way to achieve the zero-defect limit of plastic-encapsulated power devices. This limit can be reached by, first, evaluating the influence of the major components involved and, consequently, by selecting the appropriate materials and measures, and, second, by always keping in mind the interdependence between all components, i.e., chip and package have to be regarded as an entity. An important finding was that applying simply one improvement step will not necessarily lead to the desired goal. Only the implementation of all improvement steps considering their interdependence is the key for the perfect overall system chip and package. In Part III of this series of papers, the influence of passivation and die coating materials on thermomechanical damage is investigated. Finally, it is shown that an intelligent chip design, in combination with a stiff Al multilayer, a low-stress molding compound (low coefficient of thermal expansion and high Youngs modulus), a new passivation material, and an appropriate polyimide layer, may reduce the thermomechanical damage to zero, even for electronic power devices..

A simple moisture diffusion model for the prediction of optimal baking schedules for plastic SMD packages

Abstract The moisture concentration at the chip surface is the important parameter for the moisture sensitivity of the P-MQFP80 product considered here. When the critical moisture concentration at the die surface is reached, delamination occurs after soldering shock, e.g at 240°C. This critical moisture concentration, which can be determined by experiments conducted at 30°C/60% relative humidity (RH) followed by soldering shock, allows to predict the product’s moisture performance at other ambient conditions. In the case studied here, prediction was done at a customer use condition of 30°C/85% RH. Furthermore, this work showed that preconditioning of plastic packages not only induces the onset of delamination at the die surface but it appears to weaken the adhesion at this interface as well. As a result, delamination failure starts to occur earlier (i.e. within shorter moisture exposure time) in the devices tested after subsequent thermal cycling stress test. A simple moisture diffusion analytical model is proposed here for predicting the optimal baking schedules for plastic SMD packages.

On the temperature dependence of critical moisture concentration on delamination initiation in microelectronic devices

At a given soldering temperature, Ts the delamination initiation between die surface and molding compound of a P-MQFP80 plastic package is determined only by the critical moisture concentration, Ccrit at this interface. In this work, the temperature dependence of critical moisture concentration Ccrit on delaminaton initiation was investigated. Ccrit was found to decrease with increasing soldering temperature.

On the prediction of optimal baking schedules in plastic SMD microelectronic devices

Moisture concentration at the critical material interface is the key parameter as far as moisture sensitivity of a plastic package is concerned. Using a simple 1-D moisture diffusion model, this parameter allowed us to predict the optimal baking time at 125°C for P-DSO14 and MQFP80: 4-16 and 6-24, hours, respectively, depending on the considered material interface. The theoretical predictions agree well with the experimental results. On the other hand, the standard IPC/JEDED J-STD-033C recommends a distinctly longer baking time of 43 hours.