Kheng Chooi Lee

A simple model for the mode I popcorn effect for IC packages

Abstract A simple model for the Mode I popcorn effect is presented here for packages with rectangular die pad (P-DSO). A package “stability parameter”, relating to its moisture sensitivity, is derived from the popcorn model. It describes the critical factors for a robust package - molding compound properties and package, leadframe design for a given preconditioning and soldering process. Furthermore, nomograms generated from the model enable an easy estimation of moisture sensitivity levels (between 1 and 5) of packages with different die pad sizes and molding compound underpad thicknesses and for different soldering temperatures ranging from 220°C to 260°C (Pb-free soldering).

A simple moisture diffusion model for the prediction of optimal baking schedules for plastic SMD packages

Abstract The moisture concentration at the chip surface is the important parameter for the moisture sensitivity of the P-MQFP80 product considered here. When the critical moisture concentration at the die surface is reached, delamination occurs after soldering shock, e.g at 240°C. This critical moisture concentration, which can be determined by experiments conducted at 30°C/60% relative humidity (RH) followed by soldering shock, allows to predict the product’s moisture performance at other ambient conditions. In the case studied here, prediction was done at a customer use condition of 30°C/85% RH. Furthermore, this work showed that preconditioning of plastic packages not only induces the onset of delamination at the die surface but it appears to weaken the adhesion at this interface as well. As a result, delamination failure starts to occur earlier (i.e. within shorter moisture exposure time) in the devices tested after subsequent thermal cycling stress test. A simple moisture diffusion analytical model is proposed here for predicting the optimal baking schedules for plastic SMD packages.

Reliability evaluation of copper (Cu) through-silicon via (TSV) barrier and dielectric liner by electrical characterization

The purpose of this study is to analyze the failure mechanisms of copper (Cu) through silicon via (TSV) with titanium (Ti) barrier and silicon dioxide (SiO2) dielectric liner, following various stress tests such as electrical, temperature cycling (TC) and high temperature storage (HTS) via electrical characterization methods. The various stresses are performed individually or in a combination of TC or HTS with electrical bias for comparison. Capacitance-voltage (C-V) and current density-electric field (J-E) characteristics were plotted after the respective stresses, to detect any changes in its electrical characteristics. Results from C-V and J-E plots suggest that barrier degradation is related to material and structural influence. The degradation in the barrier layer can lead to Cu diffusion and drift into the dielectric layer, which is reflected by changes to the minimum depletion capacitance measured in the C-V curve. An increase or decrease in the minimum depletion capacitance measured indicates Cu ions presence in SiO2 or silicon (Si) substrate respectively. The individual stresses performed reveal that there was insignificant copper existence in the dielectric layer. However a combination of stresses which involves an additional electrical bias stress on TC or HTS sample better enabled the detection of degraded barrier by electrical means. The electrical bias serves as a driving force for Cu ions drift through degraded barrier as Cu does not readily diffuse into SiO2 at room temperature. On the other hand, by increasing the number of TSVs measured in an array structure, it is found that degraded barrier and Cu trace was detected without the need for subsequent electrical bias stress.

Non-destructive degradation study of copper wire bond for its temperature cycling reliability evaluation

Abstract Wire bonding is essential for the electrical connection of integrated circuit (IC) devices, therefore its quality and reliability is of utmost importance. During the wire bonding process, several parameters need to be well controlled in order to achieve a well bonded wire. Furthermore, the migration to copper (Cu) wire from gold (Au) due to its high cost has resulted in an even more stringent and narrow process window. Current industrial practices to evaluate wire bond quality after the assembly and packaging process are either done destructively which may result in loss of critical information, or non-destructively which are limited by resolution, cost and time. In this work, the quality of copper wire bond is being evaluated by electrical means that is non-destructive, fast and accurate. This makes it suitable for use in the production line for wire bond quality evaluation. Experimental results showed that there is a good correlation with conventional wire assessment methods. Furthermore the electrical method is sensitive enough to pick out degraded wires that conventional methods are unable to identify.

Observations of copper (Cu) transport in through-silicon vias (TSV) structure by electrical characterization for its reliability evaluation

Through-silicon via (TSV) has in recent years been actively pursued and has become one of the key enablers for three dimensional (3D) IC. However, one of the widely used filler material for TSV is copper (Cu), which readily diffuses into the dielectric layer. In this study, the monitoring of Cu ions transport within the dielectric layer is observed and controlled for its reliability assessment. Cu ions can be driven towards the silicon dioxide (SiO2) or back to the Cu bulk by applying an appropriate E-field. Time dependent dielectric breakdown (TDDB) was then performed at various conditions and it was found that the breakdown mechanism is different, dependent on the tested, E-field and temperature where Cu ions could play different roles in the dielectric. Finally the extension of TDDB lifetime was also demonstrated with appropriate control of the Cu ions, based on the understanding of the breakdown mechanism.

On the temperature dependence of critical moisture concentration on delamination initiation in microelectronic devices

At a given soldering temperature, Ts the delamination initiation between die surface and molding compound of a P-MQFP80 plastic package is determined only by the critical moisture concentration, Ccrit at this interface. In this work, the temperature dependence of critical moisture concentration Ccrit on delaminaton initiation was investigated. Ccrit was found to decrease with increasing soldering temperature.

Reliability Evaluation of Copper (Cu) Through-Silicon Vias (TSV) Barrier and Dielectric Liner by Electrical Characterization and Physical Failure Analysis (PFA)

The motivation behind this study is to detect barrier and dielectric liner degradation in a copper (Cu) through-silicon via (TSV) structure. The integrity of titanium (Ti) barrier and silicon dioxide (SiO2) dielectric liner are evaluated via a non-destructive electrical characterization method after being subjected to different stress tests such as high temperature storage (HTS), temperature cycling (TC) and electrical biasing. The various different stresses were either performed independently, or performed as a combination stress with electrical bias for comparison. After performing the respective stresses, capacitance-voltage (C-V) and current density-electric field (J-E) characteristics were analyzed to identify differences in its electrical characteristics. Degradation of the barrier liner may result in the migration of Cu from the Cu via into the dielectric liner. This is identified by changes observed in the inversion capacitance, as reflected in the C-V curve. Physical failure analysis (PFA) was performed on degraded structures and verified the presence of Cu in the dielectric due to barrier degradation as detected by the electrical measurement. It is suggested that barrier degradation leading to the migration of Cu into the dielectric liner can be associated to material and structural integrity which is dependent on the stress conditions. This understanding is useful in the reliability assessment of Cu TSV structures under various stress conditions, making it appropriate for future TSV degradation studies.

On the prediction of optimal baking schedules in plastic SMD microelectronic devices

Moisture concentration at the critical material interface is the key parameter as far as moisture sensitivity of a plastic package is concerned. Using a simple 1-D moisture diffusion model, this parameter allowed us to predict the optimal baking time at 125°C for P-DSO14 and MQFP80: 4-16 and 6-24, hours, respectively, depending on the considered material interface. The theoretical predictions agree well with the experimental results. On the other hand, the standard IPC/JEDED J-STD-033C recommends a distinctly longer baking time of 43 hours.