Peter Nelle

On the Way to Zero Defect of Plastic-Encapsulated Electronic Power Devices—Part I: Metallization

Concerning thermomechanically induced failures, such as metal line deformation and passivation cracks, there is a practicable way to achieve the zero-defect limit of plastic-encapsulated power devices. This limit can be reached by evaluating the influence of the major components involved and, consequently, by selecting the appropriate materials and measures. On the other hand, the interdependence between all components must always be kept in mind, i.e., chip and package have to be regarded as an entity. An important finding was that applying simply one improvement step will not necessarily lead to the desired goal. Only the implementation of all improvement steps considering their interdependence is the key for the perfect overall system chip and package. In Part I of this series of papers, the yield stress of the power metallization is shown to play a crucial role for the generation of metal deformation and passivation cracks. Understanding the ratcheting mechanism led to the development of a new layered metallization material with a distinctly increased yield stress, resulting in a considerably reduced failure generation.

On the Way to Zero Defect of Plastic-Encapsulated Electronic Power Devices—Part II: Molding Compound

Concerning thermomechanically induced failures, such as metal line deformation and passivation cracks, there is a practicable way to achieve the zero-defect limit of plastic-encapsulated power devices. This limit can be reached by evaluating the influence of the major components involved and, consequently, by selecting the appropriate materials and measures. On the other hand, the interdependence between all components must always be kept in mind, i.e., chip and package have to be regarded as an entity. An important finding was that applying simply one improvement step will not necessarily lead to the desired goal. Only the implementation of all improvement steps considering their interdependence is the key for the perfect overall system chip and package. In Part II of this series of papers, the thermomechanical influence of the molding compound (MC) on the chip, i.e., the root cause of metal deformation and passivation cracks, was studied in great detail. Concerning the generation of these failures, the coefficient of thermal expansion was shown to play a key role. However, for a full understanding of the thermomechanically induced damage, the viscoelastic properties of the MC have to be considered.

On the Way to Zero Defect of Plastic-Encapsulated Electronic Power Devices—Part III: Chip Coating, Passivation, and Design

Concerning thermomechanically induced failures such as metal-line deformation and passivation cracks, there is a practicable way to achieve the zero-defect limit of plastic-encapsulated power devices. This limit can be reached by, first, evaluating the influence of the major components involved and, consequently, by selecting the appropriate materials and measures, and, second, by always keping in mind the interdependence between all components, i.e., chip and package have to be regarded as an entity. An important finding was that applying simply one improvement step will not necessarily lead to the desired goal. Only the implementation of all improvement steps considering their interdependence is the key for the perfect overall system chip and package. In Part III of this series of papers, the influence of passivation and die coating materials on thermomechanical damage is investigated. Finally, it is shown that an intelligent chip design, in combination with a stiff Al multilayer, a low-stress molding compound (low coefficient of thermal expansion and high Youngs modulus), a new passivation material, and an appropriate polyimide layer, may reduce the thermomechanical damage to zero, even for electronic power devices..

Modeling of DMOS subjected to fast temperature cycle stress and improvement by a novel metallization concept

DMOS switches are subjected to severe temperature pulses during operation, which cause a thermomechanical stress and ILD cracking. The failure evolution under fast temperature cycle stress is assessed with FEM simulation. Based on these findings a novel metallization system is introduced, which extends the lifetime by three orders of magnitude.

Prediction of wafer bow through thermomechanical simulation of patterned hard coated copper films

Due to the large difference in the coefficients of thermal expansion of the materials used in advanced semiconductor manufacturing, the fabrication process of semiconductor chips leads to a wafer bow. In addition, the layers may pass through material phase changes, which generate an unwanted film stress, making the large accumulated wafer bow very difficult to handle. We have compared the wafer bow calculated from a thermomechanical finite element simulation with experiments, and developed new material models for copper and protecting layers. We have also shown how the patterning of the thin films reduces the overall wafer bow. The wafer bow has a linear dependency with respect to the coverage percentage, especially over the low coverage range. This study introduces useful hints and predicts a reduced wafer bow, which is already experimentally proved in the manufacturing process of a modern power semiconductor technology.

A new test circuit for the matching characterization of npn bipolar transistors

A new test macro with an active device array is presented for the mismatch characterization of npn bipolar transistors. The macro contains a CMOS circuit which serves for the selection of each bipolar device individually. For each bipolar device terminal a force/sense method is employed to assure the high voltage accuracy requested for bipolar transistors. The characterization of the array with transistors of different geometry gives a database on chip level for the statistical analysis. Matching parameters are given for collector current, current gain, and base-emitter voltage of a 0.5 /spl mu/m smart power technology. The results agree well with in-line measurements using single device pairs and are comparable to reported values in the literature for corresponding technologies.

Impact of alpha-radiation on power MOSFETs

In this paper it is shown how the impact of alpha particles in the gate oxide of a power MOSFET leads to a local reduction of the threshold voltage Vth. Evidence is presented that radioactive impurities in the solder material of the clip attach indeed are the root cause for such effects observed in long term measurements with electrical gate bias. Data show that alpha impacts have no negative influence on reliability and application performance of power MOSFETs.