Peter Bogner
Infineon Technologies
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Publication
Featured researches published by Peter Bogner.
norchip | 2006
Christer Svensson; Stefan Andersson; Peter Bogner
We attempt to formulate a theory for the power consumption of AD converters. The theory is based on first principles circuit theory and on the assumption of full digital error correction. The theory is compared to actual experimental converters
international solid-state circuits conference | 2011
Franz Kuttner; Harun Habibovic; Thomas Hartig; Michael Fulde; Gernot Babin; Andreas Santner; Peter Bogner; Claus Kropf; Harald Riesslegger; Uwe Hodel
Battery operation in mobile applications needs power efficient DC-DC converters which are able to handle battery voltages up to 5.5V. Normally, these DC-DC converters are built in special technologies. For decreased footprint and chip count of the overall system, a system-on-chip solution on modern CMOS technology with core supply voltages around 1V is preferred. The presented DC-DC buck converter generates 0.9 to 1.8V at output currents up to 500mA from a battery voltage of 2.4 to 5.5V with high efficiency in a high-k 28nm metal-gate CMOS technology.
european solid-state circuits conference | 2006
Peter Bogner; Harun Habibovic; Thomas Hartig
This paper describes a new circuit solution to implement a high signal swing amplifier for driving a low resistive and high capacitive load. The amplifier is dedicated to operate at a supply voltage of 2.5V driving an earpiece device of a mobile phone by the usage of a standard digital single gate oxide transistor in a 65nm technology. The high linearity is achieved by using a three stage amplifier. To handle the high voltage of 2.5 V with the 1.2 V transistor an innovative transistor cascoding is implemented. A class AB output stage is chosen to ensure a low power consumption. A prototype is realized in a low power 65 nm CMOS technology. The measured THD is lower than 0.04% at the desired audio band of 20kHz
international solid-state circuits conference | 2006
Peter Bogner; Franz Kuttner; Claus Kropf; Thomas Hartig; M. Burian; Hermann Eul
A 14b multi-bit-per-stage pipelined ADC is implemented in a 0.13mum digital CMOS process. The gain and matching errors of the analog circuitry are compensated by a digital calibration scheme that allows the usage of a low-gain op-amp. A low power consumption has been reached by introducing a charge compensation scheme
Archive | 2005
Peter Bogner
Archive | 2004
Peter Bogner
Archive | 2007
Peter Bogner
Archive | 2004
Peter Bogner
Archive | 2013
Peter Bogner
Archive | 2014
Peter Bogner; Luca Petruzzi