Hubert Rothleitner

New on-chip screening of gate oxides smart power devices for automotive applications

Efficient screening procedures for the control of the gate oxide defectivity are vital to limit early failures especially in critical automotive applications. Traditional strategies based on burn-in and in-line tests are able to provide the required level of reliability but they are expensive and time consuming. This paper presents a novel approach to the gate stress test of Lateral Diffused MOS transistors based on an embedded circuitry that includes logic control, high voltage generation, and leakage current monitoring. The concept, advantages and the circuit for the proposed built-in gate stress test procedure are described in very detail and illustrated by circuit simulation.

A new built-in screening methodology to achieve zero defects in the automotive environment

Efficient screening procedures for the control of the defectivity are vital to limit early failures especially in critical automotive applications. Traditional strategies based on burn-in and in-line tests are able to provide the required level of reliability but they are expensive and time consuming. This paper presents a novel built-in reliability testing methodology to screen out gate oxide and crystal related defects in Lateral Diffused MOS transistors. The proposed technique is based on an embedded circuitry that includes logic control, high voltage generation, and leakage current monitoring.

Design and Experimental Characterization of a New Built-In Defect-Based Testing Technique to Achieve Zero Defects in the Automotive Environment

Efficient screening procedures for the control of defectivity are vital to limit early failures, particularly in critical automotive applications. Traditional strategies based on burn-in and in-line tests are able to provide the required level of reliability, but they are expensive and time consuming. This paper presents a novel built-in circuitry to screen out gate oxide and crystal-related defects in Lateral Diffused MOS transistors. The proposed technique is based on an embedded circuitry that includes control logic, high-voltage generation, and leakage current monitoring. The concept and the advantages of the proposed screening procedure are described in detail and demonstrated experimentally in conjunction with the integration of a test chip.

A New Built-In Defect-Based Testing Technique to Achieve Zero Defects in the Automotive Environment

Efficient screening procedures for the control of the defectivity are vital to limit early failures especially in critical automotive applications. Traditional strategies based on burn-in and in-line tests are able to provide the required level of reliability but they are expensive and time consuming. This paper presents a novel built-in reliability testing methodology to screen out gate oxide and crystal related defects in Lateral Diffused MOS transistors. The proposed technique is based on an embedded circuitry that includes control logic, high voltage generation, and leakage current monitoring. The concept, advantages and the circuit for the proposed test procedure are described in very detail and illustrated by circuit simulation.

Novel built-in methodology for defect testing of capacitor oxide in SAR analog to digital converters for critical automotive applications

Mixed signal components are increasingly used to implement controlling loops and digital signal processors in automotive applications. Successive Approximation Register (SAR) analog-to-digital converters based on switched capacitors play a major role in this evolution. Since the defectivity of the intermetal dielectric in vertical parallel plate capacitors is a major concern of this technology, dedicated screening techniques are needed to implement “zero defects” strategies. A novel screening approach is proposed in this paper, which is based on the use of a dedicated embedded circuitry with very low area consumption. A design is presented, which includes the control logic, the high voltage generation, and the leakage detection circuitry. The concept, advantages and the circuits for the proposed built-in reliability test are described in detail and illustrated by layout and circuit simulations.

A new built-in screening methodology for Successive Approximation Register Analog to Digital Converters

A novel built-in approach is proposed to screen out defects in the array of capacitors and control logic of Successive Approximation Register Analog to Digital Converters. This technique is based on an embedded circuitry for the configuration, the stressing and for an accurate and fast leakage current measurement. The built-in screening system reduces the dependency on external automatic test equipment and cuts the testing time and costs. The proposed solution has been integrated on silicon for verification and characterization. The idea implies a negligible silicon area overhead because the test structure can be shared among multiple Analog to Digital Converters on the same chip.

In situ screening techniques for defective oxides in devices for automotive applications

Efficient screening procedures for the control of the defectivity are vital to limit early failures especially in critical automotive applications. Traditional strategies based on burn-in and in-line tests are able to provide the required level of reliability but they are expensive and time consuming. This paper presents novel built-in circuitries to screen out oxide defects in integrated circuits for the most important building blocks used in automotive applications. The proposed techniques are based on an embedded circuitry that includes control logic, high voltage generation, and leakage current monitoring. The concept and advantages of the proposed screening procedure are described in very detail and demonstrated experimentally in conjunction with the integration of test-chips.

Novel Solution for the Built-in Gate Oxide Stress Test of LDMOS in Integrated Circuits for Automotive Applications

Efficient screening procedures for the control of the gate oxide defectivity are vital to limit early failures especially in critical automotive applications. Traditional strategies based on burn-in and in-line tests are able to provide the required level of reliability but they are expensive and time consuming. This paper presents a novel approach to the gate stress test of Lateral Diffused MOS transistors based on an embedded circuitry that includes logic control, high voltage generation, and leakage current monitoring. The concept, advantages and the circuit for the proposed built-in gate stress test procedure are described in very detail and illustrated by circuit simulation.