Peter J. Hicks

A general-purpose processor-per-pixel analog SIMD vision chip

A smart-sensor VLSI circuit suitable for focal-plane low-level image processing applications is presented. The architecture of the device is based on a fine-grain software-programmable SIMD processor array. Processing elements, integrated within each pixel of the imager, are implemented utilising a switched-current analog microprocessor concept. This allows the achievement of real-time image processing speeds with high efficiency in terms of silicon area and power dissipation. The prototype 21 /spl times/ 21 vision chip is fabricated in a 0.6 /spl mu/m CMOS technology and achieves a cell size of 98.6 /spl mu/m /spl times/ 98.6 /spl mu/m. It executes over 1.1 giga instructions per second (GIPS) while dissipating under 40 mW of power. The architecture, circuit design and experimental results are presented in this paper.

A CMOS general-purpose sampled-data analog processing element

This work presents the architecture and implementation of an analog processor, which in a way akin to a digital microprocessor, embodies a physical model of the universal Turing machine. The analog microprocessor (A/spl mu/P) executes software programs, while nevertheless operating on analog sampled data values. This enables the design of mixed-mode systems which retain the speed/area/power advantages of the analog signal processing paradigm, while being fully programmable general-purpose systems. A proof-of-concept integrated circuit has been implemented in 0.8-/spl mu/m CMOS technology, using switched-current techniques. Experimental results from fabricated chips are presented and examples of the application of the A/spl mu/Ps in image processing are given.

An analogue SIMD focal-plane processor array

A new smart-sensor VLSI circuit intended for focal-plane processing of grey-scale images is presented. The architecture is based on a fine-grain software-programmable SIMD array. Processing elements, integrated within each pixel of the imager, are implemented utilising a switched-current analogue microprocessor concept. In a 0.6 /spl mu/m CMOS process the cell size is equal to 98.6 /spl mu/m/spl times/98.6 /spl mu/m. A prototype 21/spl times/21 array chip executes over 1.1 GIPS (Giga Instructions Per Second) while dissipating below 40 mW of power and demonstrates a real-time performance on a variety of early vision tasks.

A CMOS general-purpose sampled-data analogue microprocessor

This paper presents a general-purpose sampled-data analogue processing element that essentially functions as an analogue microprocessor (A/spl mu/P). The A/spl mu/P executes software programs, in a way akin to a digital microprocessor, while nevertheless operating on analogue sampled data values. This enables the design of mixed-mode systems which retain the speed/area/power advantages of the analogue signal processing paradigm while being fully programmable, general-purpose systems. A proof-of-concept integrated circuit has been implemented in 0.8 /spl mu/m CMOS technology, using switched-current techniques. Experimental results and examples of the application of the A/spl mu/Ps in image processing are presented.

Four Case Studies of Adapting Enquiry-Based Learning (EBL) in Electrical and Electronic Engineering

Four different instances of enquiry-based learning (EBL), developed in a School of Electrical and Electronic Engineering, are described. Key decisions in the design of these activities are detailed, emphasising flexibility in approach. Although the activities took place in broadly the same environment, the local contexts required subtle tailoring. The design decisions taken in each case are described and general overviews from integrative evaluations are provided. An emergent distinction between the forms of EBL developed was between those that focused on generic or specific skills and those that focused on content knowledge; these may be termed project-based learning and problem-based learning respectively. The influence of the focus of the activity on the design decisions is described.

A FAST AND FLEXIBLE MULTICHANNEL ELECTRON DETECTOR WITH PARALLEL READOUT FOR PHOTOELECTRON SPECTROSCOPY

To satisfy end user requirements for higher throughput and reliability in photoelectron spectroscopy, a new multichannel electron detector with discrete electronics has been designed and commissioned at Daresbury Laboratory. Count rate performance has been enhanced by the use of low resistance microchannel plates which amplify the electron pulses incident on the anode array. The low resistance microchannel plates are linear to 2.5 × 104 s−1 mm−2 for a bias voltage of 900 V per plate, providing more than an order of magnitude improvement in count rate performance over high resistance microchannel plates, microchannel plate outgassing in the ultra-high vacuum environment limits the scale of this improvement. A novel anode design maximizes the collection efficiency, while minimising crosstalk between channels (< 0.6% after discrimination) and provides up to 40 parallel channels on a 1 mm pitch. The collection efficiency is increased from 50% to 70% (for the present geometry) by applying a 50 V bias between the guard rail and electrodes on the anode. Each data collection channel comprises a fast current amplifier and discriminator, capable of a throughput of 2.5 × 107 s−1, and a 24 bit scaler. The integral non-linearity for flat-field illumination is better than 10% with no correction. The fast multichannel detection system gives a throughput enhancement of 10–20 on single-channel detection systems. It has also proved to be significantly better than previous multichannel detection systems with discrete electronics due to its high throughput, modular design and flexible structure.

A Practical Approach to Digital Integrated Circuit Design Using Uncommitted Logic Arrays

Uncommitted logic arrays or gate arrays provide a fast and cost-effective means of producing digital L.S.I, circuits. Their increasing popularity has created a need for engineers who are skilled in this new technology. Students on a one-year M.Sc. course are able to gain practical experience of logic design using gate arrays and are motivated by the opportunity to characterise and test the finished product.

Development of high-throughput flexible multichannel electron detectors at Daresbury Laboratory.

Continuing demands from Synchrotron Radiation Source (SRS) end-users for higher throughput and improved reliability in photoelectron spectroscopy experiments have driven an intensive development programme for new multichannel electron detectors. The development philosophy focuses on high throughput to match present and future source intensity, flexible structures to allow increased mobility of designs and modular design for easy maintenance and repair. Developments include parallel readout electronics and innovative detector heads for the hemispherical deflection analysers currently in use on the SRS. Novel anode arrays have been implemented in the detector heads and extensive microchannel plate (MCP) characterization has been undertaken to source the MCPs most suited to this application. The present multichannel detection systems provide a significant enhancement to single-channel detection systems. They have also surpassed previous multichannel detection systems due to their high throughput, flexible structure and modular design. Information on these developments and experimental results obtained at Daresbury Laboratory are presented.