Peter M. Lee

Simulation of MOSFET lifetime under AC hot-electron stress

A substrate current model and a quasistatic hot-electron-induced MOSFET degradation model have been implemented using the Substrate Current And Lifetime Evaluator (SCALE) package. It is shown that quasistatic simulation is valid for a class of waveforms that includes those encountered in inverter-based logic circuits. The validity and limitations of the model are illustrated with experimental results. SCALE is linked to SPICE externally in a pre- and postprocessor fashion to form an independent simulator. The preprocessor interprets the input deck and requests SPICE to output the transient node voltages of the user-selected devices. The postprocessor then calculates the transient substrate current and makes a lifetime prediction. >

Circuit aging simulator (CAS)

A circuit aging simulator (CAS) has been developed as part of the BSIM (Berkeley Short-channel Igfet Model) family to predict the effects of hot-electron degradation on MOS circuit behavior. Using the SPICE2 of SPICE 3 circuit simulator in a UNIX environment, CAS simulates circuit behavior at a user-specified future time using fresh and DC prestressed BSIM parameter process files. CAS is configured in a pre- and postprocessor configuration, so that no modifications to the SPICE code are necessary. Iterative simulation to take into account ongoing degradation can also be done through an accompanying UNIX shell scrip program.<<ETX>>

Circuit reliability simulator-oxide breakdown module

A computer program which generates statistics about circuit failures due to MOS oxide breakdown has been developed. The program, CORS (Circuit Oxide Reliability Simulator), predicts the probability of circuit failure as a function of operating time, temperature, power supply voltage, and input waveforms. It consists of a preprocessor and postprocessor for SPICE. CORS calculates the probability of failure by using the node voltages provided by SPICE and oxide defect statistics provided by the user. The effect of burn-in on oxide reliability can also be simulated. CORS is linked to a hot electron and an electromigration reliability simulator. Simulation results are presented.<<ETX>>

Relating CMOS inverter lifetime to DC hot-carrier lifetime of NMOSFETs

The authors report that comparison with measured 75-MHz CMOS ring-oscillator speed degradation suggests that quasi-static circuit aging simulations using DC stress data do not underestimate circuit degradation. Roughly speaking, 10% degradation in NMOSFET linear current results in only about 1.3% increase in CMOS inverter propagation delay. This 10% current degradation occurs in an inverter-based circuit over a time that is about six times the MOSFET DC lifetime at maximum I/sub sub/ and about 30 times the DC lifetime at maximum I/sub sub//sup 3//I/sub ds//sup 2/.<<ETX>>

Simulating the competing effects of P- and N-MOSFET hot-carrier aging in CMOS circuits

A PMOSFET hot-carrier degradation model has been incorporated into the reliability simulator BERT-CAS, enabling prediction of dynamic circuit-level degradation in which both PMOSFET and NMOS-FET degradation play a major role. Comparisons with measured data from CMOS ring oscillator frequency shifts show that full aging simulation by CAS can correctly predict the initial frequency increase due to the PMOSFET current enhancement, and the eventual frequency decrease due to the NMOSFET current degradation. >

Quasi-static simulation of hot-electron-induced MOSFET degradation under AC (pulse) stress

A substrate current model and a quasi-static hot-electron-induced MOSFET degradation model have been implemented in the Substrate Current and Lifetime Evaluator (SCALE). It is shown that quasi-static simulation is valid for a class of waveforms including those encountered in inverter-based logic circuits. The validity and limitations of the model are illustrated with experimental results. SCALE is linked to SPICE externally in a pre- and post- processors fashion to form an independent simulator. The pre-processor interprets the input deck, and requests SPICE to output the transient node voltages of the user-selected devices. The post-processor then calculates the transient substrate current and makes lifetime prediction.

Simulation of P- and N-MOSFET hot-carrier degradation in CMOS circuits

A PMOSFET hot-carrier degradation model has been incorporated into the reliability simulator BERT-CAS, enabling prediction of dynamic circuit-level degradation in which both PMOSFET and NMOSFET degradation play a major role. Comparisons are presented which reveal the good fit obtained between measurement and simulation results.<<ETX>>

BSIM-CG: A compact model of cylindrical gate / nanowire MOSFETs for circuit simulations

A full-fledged surface potential based compact model for cylindrical gate transistors replete with physical effects such as polysilicon gate depletion, mobility degradation, quantum mechanical effects, short channel effects, leakage currents, and parasitic resistances and capacitances etc. is presented. For the first time we present calibration results of such a model to a cylindrical gate technology that exhibits asymmetric i-v characteristics.