Peter Noel

Recent advances in high-speed serial I/O trends, standards and techniques

The goal of this paper is to provide the reader with an overview of the recent advances (in the past year) made in the industry with respect to high-speed data transport. The latest developments in the industrys main high-speed I/O protocols and the attempted standardization of the high-speed physical interface are presented. In reviewing these advanced techniques, examples will use the basic circuit-level building blocks within a high-speed serial transceiver and will give the basics behind the design techniques required to successfully design and implement a typical multi-Gigahertz serial I/O device

Implementing a digitally synthesized adaptive pre-emphasis algorithm for use in a high-speed backplane interconnection

This paper presents a novel implementation technique using simple digital ASIC synthesis to generate a silicon layout of a multi-level PAM modulation circuit that incorporates a digitally adaptive pre-emphasis scheme. While computationally complex, the actual VLSI implementation is relatively simple, requires minimal power and generates a layout that minimizes the footprint. The results of the digital synthesis of several comparable adaptive circuits are detailed and compared. Several devices have been submitted for fabrication, via CMC, using the TSMC 0.18 /spl mu/m CMOS generic standard cell process.

PLL-based fractional-N frequency synthesizers

Recent trends in the commercial use of fractional-N frequency synthesis can be attributed to the characteristic of independent loop bandwidth-channel spacing that results in low phase noise and relaxes the phase-locked loop (PLL) design constraints. This paper reviews several techniques used to implement fractional-N frequency synthesizers and discusses the advantages and disadvantages. It also addresses design options and associated trade-offs.

An overview of high-speed serial I/O trends, techniques and standards

The paper provides a brief overview of the basic building blocks within a high-speed serial transceiver, provides an outline of the major interconnect standards utilizing the highspeed serial I/O circuitry and gives the basics behind the design techniques required to design and implement a typical multi-GHz serial I/O device successfully. Several major design obstacles are presented, followed by a discussion of the potential design techniques that may be used to overcome such implementation issues. The paper covers two main design approaches: low swing differential signaling and multilevel signaling.

Doubling the through-put of a Digital Microwave Radio system by the implementation of a cross-polarization interference cancellation algorithm

Digital Microwave Radio communications is not a new commercial theatre but is an area that is fostering several novel implementations of older ideas. The present application for Digital Microwave Radio is for use in the backhaul of high-speed data and digitized voice and video communications. This single channel implementation operates as a point-to-point radio link on carrier frequencies from 6 to 38 GHz, each operating at data rates of up to 500 Mbps. Faced with limited spectrum but increased demand for doubling of data rates the use of orthogonally polarized channels has been incorporated. By using the same carrier frequency for two channels, simultaneously, while incorporating orthogonal polarization, allows a doubling of data rate yet not increasing the required width of RF spectrum.

The design, development and implementation of a cross-polarization interference cancellation system for point-to-point Digital Microwave Radio systems

Digital Microwave Radio communications is not a new commercial theatre but is an area that is fostering several novel implementations of older ideas. The DragonWave application for Digital Microwave Radio is for use in the backhaul of high speed data and digitized voice communications. This implementation is available as a point-to-point radio link on various GigaHertz carrier frequencies operating at data rates upto 500 Mbps. Faced with demand from customers requiring doubling of data rates while not increasing the channel bandwidth, the use of orthogonally polarized channels has been incorporated. Such cross-polarized co-channel operation is not without its issues, one of which is environment induced cross-polarization interference (XPI). To reduce the effects of XPI on a DragonWave point-to-point radio link, an cross-polar interference cancellation (XPIC) system has been conceived and implemented The implementation of DragonWaves XPIC feature meets or exceeds performance levels specified in ETSI EN 302–217–2–1 [1] standard as a result of to some unique interference-synchronization features (patent pending).

A reduced signal feed-through 6-tap pre-emphasis circuit for use in a 10GB/S backplane communications system

The current mode digital-to-analog converter (iDAC) has been widely used in finite-impulse response (FIR) filter implementations as it is well-suited for high-speed operation. This paper proposes a novel solution to reduce the signal feed-through problem commonly encountered in current mode digital-to-analog converters in pre-emphasis circuits. To improve the eye opening, the circuit must be able to limit the flow of feed-through signal to the summing node. The proposed multi-tap pre-emphasis circuit has been simulated using an IBM 130nm CMOS technology.

On /spl Delta//spl Sigma/ fractional-N frequency synthesizers

/spl Delta//spl Sigma/ fractional-N frequency synthesis achieves low phase noise performance while relaxing the phase-locked loop (PLL) design constraints and reduces the desired channel spacing. This paper reviews the recent advanced techniques on the implementation of fractional-N frequency synthesizers and discusses their advantages and disadvantages. It also addresses the design options and the associated trade-offs.

An overview of reconfigurable VLSI based signal processing building blocks for next generation wireless devices

The introduction of advanced features in mobile communications services requires improvements upon current hardware design and verification methods. The implementation of higher bandwidth features, such as streaming video, on-demand video conferencing, etc., dictates that the wireless hardware used in the eventual deployment of next generation (fourth generation or 4G) wireless devices must evolve significantly to provide the expected quality of service (QoS) while minimizing device size and power consumption. The paper outlines the potential digital building blocks of an advanced wireless communication system, incorporating reconfigurable logic principles, suitable for consideration in the development of next generation wireless systems.

Symbol-spaced delay circuit design with half-rate clock timing for multi-taps FIR filter as pre-emphasis

A FIR filter for pre-emphasis has been used to counteract inter-symbol interference (ISI) in high-speed backplane data transmission. A novel circuit design for retiming data using a half-rate clock for the taps of a FIR filter is proposed. HSPICE simulation results for CMOS 0.18 mum technology verify that the jitter of PRBS15 (215 - 1) data at rate of 6.25 Gbps with a pre-emphasis value of 50% can be reduced to approximately 14 psec and thereby alleviating the requirement on clock frequency