Peter Pistek

Digital System Description Knowledge Assessment

The paper presents a knowledge assessment approach developed for support of Digital system description course. In the course the students should comprehend the methods and techniques used in digital system design, and gain the skills in digital systems modelling using hardware description languages (HDL). For many years the course exams used to be done only in pen and paper form. The students hated writing HDL programs on paper and the teachers disliked correcting the programs on paper as well. What is more, this type of exam has not allowed the verification of the student’s ability to debug the created model, which is the substantial part of the student’s practical skills. That is why, some years ago, we concentrated our work on designing a knowledge assessment system that will enable reliable evaluation of practical skills in the area of digital system description without substantial teacher involvement. Several applications have been developed and tested in the course. One of the best will be presented here.

Binary decision diagram optimization method based on multiplexer reduction methods

In VLSI circuit synthesis, multiplexers are widely used as a basic building element because of their ability to perform any Boolean function. Since multiplexers form a significant part of total circuit area, designers often focus on application of various optimizations. Multiplexer optimization techniques result in significant improvement in performance, area and power consumption of synthetized VLSI circuits. One of such approaches is the use of BDD as a structural representation of a multiplexer tree along with BDD optimization methods. We proposed a novel BDD optimization algorithm combining residual variable with basic BDD reduction methods. Experimental results show that implemented algorithm reduces total amount of multiplexers in optimized multiplexer tree by a minimum of 74.19% compared to a non-optimized multiplexer tree. The residual variable method provides approximately 50% reduction, what is further improved by up to additional 17.65% using basic BDD optimization methods.

Faster synthesis of combinational logic based on multiplexer trees and binary decision diagrams

Multiplexers are well known as a basic building element of digital and mixed signal circuits thanks to their ability to perform any Boolean function. Optimization is a significant part of synthesis of combinational logic, since performance has to be improved, area and power consumption have to be reduced. The paper presents a novel faster optimization method for multiplexer trees using basic BDD reduction methods, residual variables, a hash table and top-down approach. An option to automatically replace some multiplexers in the multiplexer tree with basic logic gates has been added in order to achieve better results. This method also works with multiple Boolean functions at once so that we can design circuits with more than one output. Experimental results show that implemented algorithm reduces total amount of multiplexers in optimized multiplexer tree by up to 99,99% in comparison to non-optimized multiplexer tree. In addition up to 63,46% of multiplexers can be replaced with a logic gate OR, AND or XOR, which can reduce total amount of transistors needed to realise given combinational logic by up to 24,23%.

Logical Circuits Design Education Based on Virtual Verification Panel

The paper presents a novel method for teaching courses about logical circuits. Attracting students’ interest is an issue that is being addressed in all courses. In general, students are more interested in doing practical exercises then learning theory and calculating or designing things on a piece of paper. In courses devoted to logic circuits design it is especially important that the students have the possibility to verify their designs and to experiment with various variations. Using universal virtual verification panel, the lessons can be more understandable. Our solution has limitation for logical gates as formerly had physical verification panels but also many other features which can be used during education. Experimental results show, that 90.2 % of students think that our solution is better than the old one [1].