Lukas Kohutka

Task scheduler for dual-core real-time systems

This paper presents the design of a coprocessor that performs conflict-free task scheduling for dual-core real-time systems. The solution proposed in this paper is based on two algorithms: Earliest Deadline First (EDF) algorithm that is proved to always find an optimal ordering of hard real-time tasks and the priority-based FIFO algorithm that is suitable for non-real-time tasks. The proposed coprocessor can efficiently handle any combination of both types of tasks even though they use different parameters for scheduling. Thanks to HW implementation of the scheduler, the operations are performed in one clock cycle regardless of the current and the maximum number of tasks in the system. The proposed coprocessor is optimized for dual-core CPUs, which can lead to higher performance of real-time embedded systems. Two different approaches for dual-core systems are proposed: semaphore approach and simultaneous processing approach. The simultaneous approach allows the coprocessor to accept and perform both instructions of both CPU cores simultaneously without any conflicts. Both approaches were verified using simplified version of UVM and applying 16 million instructions with randomly generated deadline values. Achieved synthesis results are discussed.

Improved Task Scheduler for Dual-Core Real-Time Systems

This paper presents the design of an improved coprocessor that performs conflict-free task scheduling for dual-core real-time systems. The solution proposed in this paper is based on two algorithms: Earliest Deadline First (EDF) algorithm that is proved to always find an optimal ordering of hard real-time tasks and the priority-based FCFS algorithm that is suitable for non-real-time tasks. The proposed coprocessor can efficiently handle any combination of both types of tasks even though they use different parameters for scheduling. Thanks to HW implementation of the scheduler, the operations are performed in one clock cycle regardless of the current and the maximum number of tasks in the system. The proposed coprocessor is optimized for dual-core CPUs, which can lead to higher performance of real-time embedded systems. Two different approaches for dual-core systems are proposed: semaphore approach and simultaneous processing approach. The simultaneous approach allows the coprocessor to accept and perform both instructions of both CPU cores simultaneously without any conflicts. Both approaches were verified using simplified version of UVM and applying 128 million instructions with randomly generated deadline values. Chip area costs are reduced by up to 35% by performing time precision optimization. The total power consumption is theoretically reduced by up to 50% during the time when the coprocessor is not used by any CPU because the dynamic power consumption is reduced dramatically.

A new efficient sorting architecture for real-time systems

This paper presents the design of a coprocessor that performs data sorting for min/max queues in real-time systems. Sorting architecture is based on systolic array architecture and heapsort algorithm. The proposed architecture, called Rocket Queue, is able not only to sort all items according to their sort values, but it is also possible to remove any item from the structure according to its unique ID, which is an important feature for many various applications. Instructions of the Rocket Queue architecture are performed in two clock cycles regardless of the number of items in the system and regardless the queue capacity. The developed coprocessor is optimized for low chip area costs, which leads to lower energy consumption too. The Rocket Queue architecture has constant time complexity, constant critical path length and it is highly predictable, thus also suitable for real-time applications. The architecture was verified using simplified version of UVM and applying millions of instructions with randomly generated sort values. Achieved synthesis results are presented and discussed. These results are significantly better than the results of systolic arrays. More than 41% of logic resources can be saved using the Rocket Queue architecture.

Rocket Queue: New data sorting architecture for real-time systems

This paper presents the design of a coprocessor that performs data sorting for min/max queues in real-time systems. The proposed architecture is based on shift registers, systolic arrays and heapsort algorithm. Such an architecture, called Rocket Queue, is able not only to sort items according to their sort values, but it is also possible to remove any item from the structure according to its unique ID, which is important for many various applications. Instructions of the Rocket Queue architecture are performed in two clock cycles regardless of the number of items in the system and regardless the queue capacity. The developed coprocessor is optimized for low chip area costs, which leads to lower energy consumption too. The Rocket Queue architecture has constant time complexity, constant critical path length and it is highly predictable, thus also suitable for real-time applications. The architecture was verified using simplified version of UVM and applying millions of instructions with randomly generated sort values. Achieved synthesis results are presented and discussed. These results are significantly better than the results of systolic arrays. More than 41% of logic resources can be saved using the Rocket Queue architecture.

Design of digital systems — A challenge towards new study programs

A new study program specialized in design of digital systems has been identified as a need. Therefore, a proposal for it was done in this paper. The most of the existing study programs are too focused on either analog circuits or software development. The proposed study program contains enough courses related to digital ASIC and FPGA development in order to meet the actual requirements of career position in this field. All important courses have been listed and described as well. One of the advantages of the proposed study program is the ability to reuse most of the courses from already existing study programs. Some courses of Electrical Engineering study programs and others of Computer Engineering or Computer Science can be effectively combined and reused. The proposed study program serves as a basic recommendation for better preparation of students who plan to start their career in the field of digital system design. Positions belonging to digital systems include, for example, ASIC Engineer, FPGA Engineer, Verification Engineer, ASIC/FPGA Test Engineer, System Engineer, Embedded Software Engineer or ASIC/FPGA Project Manager.

Faster synthesis of combinational logic based on multiplexer trees and binary decision diagrams

Multiplexers are well known as a basic building element of digital and mixed signal circuits thanks to their ability to perform any Boolean function. Optimization is a significant part of synthesis of combinational logic, since performance has to be improved, area and power consumption have to be reduced. The paper presents a novel faster optimization method for multiplexer trees using basic BDD reduction methods, residual variables, a hash table and top-down approach. An option to automatically replace some multiplexers in the multiplexer tree with basic logic gates has been added in order to achieve better results. This method also works with multiple Boolean functions at once so that we can design circuits with more than one output. Experimental results show that implemented algorithm reduces total amount of multiplexers in optimized multiplexer tree by up to 99,99% in comparison to non-optimized multiplexer tree. In addition up to 63,46% of multiplexers can be replaced with a logic gate OR, AND or XOR, which can reduce total amount of transistors needed to realise given combinational logic by up to 24,23%.