Peter Smeys

Analysis of Integrated Solenoid Inductor With Closed Magnetic Core

The effect of a closed magnetic core structure on an integrated inductor was investigated by winding two series connected inductors around a stretched hexagonal ring of CoTaZr. The 8.5 and 17.5 turn inductors were fabricated using standard silicon process, and simulations were performed using Ansoft HFSS software. The resulting inductance of the device showed no improvement over two inductors without the closed magnetic cores, indicating that the closed core structure was insufficient to enhance the mutual inductance between the two devices. This was attributed to the uniaxial anisotropy of the magnetic film, which prevented the film from routing the generated flux circularly around the core. Therefore, while the physical shape of the magnetic film was closed, the effective magnetic shape maintained an air gap.

Ultra-Compact Power Conversion Based on a CMOS-Compatible Microfabricated Power Inductor with Minimized Core Losses

A CMOS-compatible microfabricated inductor is presented. The inductor consists of a planar spiral coil optionally sandwiched between upper and lower magnetic core layers. Core materials investigated include ferrite-filled polymer and electrodeposited nickel-iron permalloy (Ni0.80Fe0.20).Four core constructions were investigated: air-core (i.e., no magnetic material); lower permalloy core with upper air core; lower permalloy core with upper ferrite polymer core; and lower and upper permalloy core. In all cases with magnetic cores, a nominal magnetic air gap of 2 microns was utilized. As expected, the all-permalloy construction yielded the highest inductance. Inductors were characterized both by impedance analysis as well as in a prototype buck DC-DC conversion circuit. When the converter was operated at 5 MHz, peak efficiency of 82% and an efficiency of 80% at a load current of 2.5 A and output voltage of 2 V was obtained.

Electroplated Metal Buried Interconnect and Through-Wafer Metal-Filled Via Technology for High-Power Integrated Electronics

In this paper, we present the design, fabrication process, and experimental results of an electroplated metal buried interconnect and through-wafer via technology suitable for extremely low resistance interconnection of microelectronic devices. The technology is demonstrated using a 3-D daisy-chain test structure comprised of electroplated through-wafer vias buried in the silicon substrate to form the respective interconnect. In contrast to the conventional daisy-chain structures used in flip chip joining and packaging, the designed structure is fabricated on a single substrate without requiring a subsequent bonding process. The top connectors formed on the front-side of the substrate are connected to bottom connectors buried inside the substrate (buried interconnects) through 61-mum-high, void-free, fully-filled, electroplated vias. The metal electroplated buried interconnects are fabricated at the bottom surface of 232-mum-deep trenches formed on the backside of the substrate. Processes for forming deep trenches with rounded-off edges and photoresist spray coating have been developed to fabricate the buried interconnects and complete the daisy-chain structure. Developed processes enable conformal photoresist deposition inside the deep vertical trenches with excellent step and sidewall coverage, surpassing the limitations of conventional fabrication approaches. Furthermore, electroplating molds were perfectly patterned at the bottom of these deep trenches. Through-wafer vias with controllable height are fabricated by direct bottom-up plating from the buried interconnect without additional preparation, such as wafer bonding or hole filling processes. The interconnection scheme developed in this research considerably reduces the height of narrow vertical vias, compared to conventional through-wafer vias, and enables a high density array of interconnect structures. Moreover, low resistance interconnect suitable for high power applications can be realized with thick electroplated copper and fully-filled vias. Buried interconnect can be also utilized in high voltage transistor applications. Resistance testing has been performed to validate the electrical integrity of the fabricated daisy-chain structure, and the results are compared with simulation and analytical calculations.

CMOS-compatible back-end process for in-plane actuating ferromagnetic MEMS

We have designed, fabricated, and tested in-plane actuating ferromagnetic MEMS switches and solenoidal inductors, which were produced using a CMOS-compatible back-end process. This process creates compact high-performance devices without high temperature processes (<; 400°C) or etching into the plane of the wafer.