Peter V. Gray

The insulated gate transistor: A new three-terminal MOS-controlled bipolar power device

A new three-terminal power device, called the insulated gate transistor (IGT), with voltage-controlled output characteristics is described. In this device, the best features of the existing families of bipolar devices and power MOSFETs are combined to achieve optimal device characteristics for low-frequency power-control applications. Devices with 600-V blocking capability fabricated using a vertical DMOS process exhibit 20 times the conduction current density of an equivalent power MOSFET and five times that of an equivalent bipolar transistor operating at a current gain of 10. Typical gate turn-off times have been measured to range from 10 to 50 µs.

The insulated gate rectifier (IGR): A new power switching device

A new power semiconductor device called the Insulated Gate Rectifier (IGR) is described in this paper. This device has the advantages of operating at high current densities while requiring low gate drive power. The devices exhibit relatively slow switching speeds due to bipolar operation. The results of two dimensional computer modelling of the device structure are compared with measurements taken on devices fabricated with 600 volt forward and reverse blocking capability.

A 600-volt MOSFET designed for low on-resistance

A 600-V vertical power MOSFET with low on-resistance is described. The low resistance is achieved by means of achieving near-ideal drain junction breakdown voltage and reduced drain spreading resistance from the use of an extended channel design. The various tradeoffs inherent in the design are discussed. Both calculated and experimental data are presented. The remote source configuration of the experimental device is also discussed.

Refractory metal silicon device technology

Abstract Films 2000–5000 A thick of Mo or W deposited over thin films of thermally grown SiO 2 are shown to be effective high temperature diffusion masks against both phosphorous and boron. These metal films may be precisely patterned and their diffusion masking properties can be used to define the source and drain regions of MOSFETs. In this manner, self-registered MOSFETs can be fabricated with a portion of the diffusion masking metal film acting as the gate electrode. Using P or B doped deposited glasses as diffusion sources, n or p channel enhancement mode MOSFETs were made by diffusion through the exposed thin SiO 2 film into p and n type Si to form source and drain junctions. Contact was subsequently made by etching holes through the oxide layers to the source and drain regions and to the refractory metal gate electrode buried within the oxide layers. These devices exhibit channel mobilities between 200 and 300 cm 2 /V-sec at gate voltages about 10 V above threshold. The stability of MOS structures processed in a similar manner has been measured. After being stressed at ±6 × 10 5 V / cm and 250°C for 15 hr, these devices exhibited shifts in their CV characteristics less than 200 mV.

FREEZE‐OUT CHARACTERISTICS OF THE MOS VARACTOR

Experimental MOS C(V) data are obtained in the temperature range over which majority carriers are substantially frozen out (40° − 70°K). These are compared with calculated curves and other calculated curves are presented to show the effect of impurity concentration and compensation. The C(V) curves are characterized by a secondary minimum in capacitance near the flat band bias.

25 amp, 500 volt insulated gate transistors

The concept of merging MOS gating with bi-polar current conduction to create a new family of power semiconductor devices with superior electrical characteristics was reported at last years conference (1). This paper will report the development of an improved device structure which enables increasing the operating current density even further so that the insulated gate transistors (IGTs) can be operated at current densities of over 200 Amperes per cm2, i.e., at over 20 times that of the power MOSFET. As discussed in Reference (1), the maximum operating current density is limited by the latch-up of a parasitic thyristor inherent in the device structure. Using two dimensional computer modelling, it has been shown that this latch-up can be suppressed by reducing the lateral sheet resistance of the p-base. This has been experimentally achieved by the addition of a high concentration boron diffusion in the DMOS cells. The electrical characteristics of 25 Amp, 500 Volt IGT devices designed and fabricated using the modelling results will be presented. These devices have the highest power handling capability (12.5 kVA) achieved in power MOS devices to date.

A large-area power MOSFET designed for low conduction losses

A new power MOSFET has been fabricated that conducts 75 A with an on-state resistance of 0.012 Ω and blocks 60 V. The device may be used as a low-loss synchronous rectifier in efficient high-frequency power supplies or as a high-current power switch in applications such as emitter switching. The device design criteria include obtaining the largest possible fraction of the ideal blocking voltage and obtaining the minimum on-State resistance. Efficient utilization of the device area requires smaller feature size and shallower junction depths for low-voltage power MOSFETs than for high-voltage ones. The device reported on is 300 mils on a side and contains over 60 000 MOSFET cells in parallel. It has a gate width of more than 4 m. This device is larger and more complex than any previously reported power MOSFET. It provides an example of how power device processing techniques are approaching those of LSI circuit technology.

A self-aligned short process for insulated-gate bipolar transistors

An n-channel vertical insulated-gate bipolar transistor (IGBT) process which implements a self-aligned p/sup +/ short inside the DMOS diffusion windows is proposed and demonstrated experimentally. The salient feature of the new process is the placement of a poly-Si plug to define the diffusion window of the p/sup +/ short. Similar forward conduction characteristics and tradeoffs with turn-off time were obtained for these self-aligned short IGBTs when compared to conventional IGBTs with non-self-aligned shorts. With a resistive load and no external gate resistor, dynamic latching current was seen to increase with increasing p/sup +/ diffusion depth and electron irradiation dosage, as well as with larger p/sup +/ diffusion windows. >

A large area power MOSFET designed for low conduction losses

A new power MOSFET that is designed to conduct 60 amperes with an on-state resistance of .014 ohms and block 60 volts has been fabricated. The device is used as a low loss synchronous rectifier in an efficient high frequency power supply. Several of the device design criteria include obtaining the largest possible fraction of the ideal blocking voltage and obtaining the minimum on-state resistance. Efficient utilization of the device area requires smaller feature size and shallower junction depths on low voltage power MOSFETs than on high voltage ones. The device reported on is 300 × 300 mils and contains over 60,000 MOSFET cells in parallel. It has a gate length of more than four meters per chip. This device is larger and more complex than any previously reported power MOSFET. It provides an example of how power device processing techniques are approaching those of LSI circuit technology.

A self-aligned short process for insulated gate transistors

A new IGT process which implements a self-aligned short is proposed and demonstrated experimentally. The salient feature of the new process is the placement of a poly-Si plug to define the diffusion window of the P+ short. Similar forward conduction characteristics and tradeoffs with turn-off time were obtained for these self-aligned short IGTs when compared to conventional IGTs with nonself-aligned shorts. With a resistive load and no external gate resistor, dynamic latching current was seen to increase with increasing P+ diffusion depth and electron dosage.