B.J. Baliga

n-channel lateral insulated gate transistors: Part I—Steady-state characteristics

The basic physics of the steady-state characteristics of the lateral insulated gate transistor (LIGT) is discussed. Results from a tWo-dimensional computer simulation Of representative LIGT structures are presented. Several Structural and process enhancements to the basic LIGT structure to increase the current handling capability and suppress latchup are pointed out. Experimental results of the steady-state characteristics of a variety of LIGT test structures are presented and analyzed. The static latching aspect of LIGT is discussed insome detail. LIGT devices employing either a buried layer or surface shorts are shown to current limit rather than latching up.

The MOS depletion-mode thyristor: a new MOS-controlled bipolar power device

A new MOS-bipolar power device in which forced-gate turn-off is achieved using a depletion region formed by an MOS gate structure is described. This device, called the depletion-mode thyristor (DMT), offers many highly desired features for high-voltage power switching applications: a) low ON-state drop, b) high input impedance, c) three-terminal operation, d) equivalent complementary devices, and e) high maximum controllable current. Experimental verification of device operation has been achieved using a UMOS gate technology. >

A 50-V, 0.7-m Omega *cm/sup 2/, vertical-power DMOSFET

A 50-V vertical power MOSFET with extremely low specific on resistance is reported. Devices with a cell density as high as 8 million cells/in/sup 2/ and capable of switching 160 A of current have been successfully fabricated using an improved fabrication technology which used low processing temperatures, double-layer interlevel dielectric, shallow source implants, and an improved source contact metallurgy. The lowest measured specific on resistances are 0.8 and 0.7 m Omega *cm/sup 2/, respectively, under continuous and pulsed bias conditions for FETs capable of blocking 50 V in the reverse direction. This result represents the best ever reported forward conductivity for a 50-V power MOSFET.<<ETX>>

Blanket LVD tungsten silicide technology for smart power applications

A high-frequency power MOSFET structure fabricated using blanket deposited LPCVD (low-pressure chemical vapor deposition) WSi/sub 2/ gate and selectively deposited LPCVD tungsten source contact metallurgy is reported. A high-density power MOSFET technology suitable for smart power applications which simultaneously lowers the gate sheet resistance and source contact resistance is discussed. This technology was used to fabricate 30-V and 50-V power FETs with excellent high-frequency performances. The measured specific on-resistance R/sub sp/, specific input capacitance C/sub sp/, and switching times are among the lowest reported in the literature for any power FET structure in this reverse blocking voltage range.<<ETX>>

The effect of substrate doping on the performance of anode-shorted n-channel lateral insulated-gate bipolar transistors

The performance of n-channel lateral-insulated-gate bipolar transistors (n-LIGBTs) with anode shorts on p/sup -/ epi/p/sup +/ substrates is compared to that of anode-shorted n-LIGBTs on p/sup -/ substrates, as well as to that of conventional n-LIGBTs on either substrate. It is shown that both forward-voltage drop and turn-off time are better for anode-shorted devices fabricated on p/sup -/ epi/p/sup +/ substrate than for those on p/sup -/ substrates, due to a larger percentage component of vertical bipolar current and a lower collector resistance. Forward-voltage drops of 3.05 and 3.3 V at 133 A/cm/sup 2/ and turn-off times of 400 and 750 ns have been measured for devices on p/sup -/ epi/p/sup +/ and p/sup -/ substrates respectively. All the LIGBTs showed current limiting at two to four times the ON-state conduction current during dynamic switching.<<ETX>>

Optimized silicon low-voltage power MOSFET's for high-frequency power conversion

The specific results obtained from a systematic optimization of low-voltage silicon power MOSFET technologies are discussed. The areas discussed include system impact, unit cell optimization, device and process modeling, fabrication technology development, and measured results. The device technologies optimized include 30 V, 50 V, and 100 V vertical power DMOSFETs with refractory silicide gate and contact metallizations. Devices with the lowest specific on-resistance, the lowest specific input capacitance, and optimized switching performance have been fabricated with excellent wafer yield. These results represent the best high-frequency switching performance based on silicon material technology ever reported.<<ETX>>

Formation and properties of rapid thermally annealed TiSi2 on lightly doped and heavily implanted silicon

Detailed material and electrical characteristics of rapid thermally annealed (RTA) TiSi2 on doped silicon are presented using transmission electron microscopy, Rutherford backscattering spectrometry, secondary ion mass spectrometry (SIMS), Auger analysis, and four‐point probe measurements. TiSi2 films with varying sheet resistances were formed on lightly doped and heavily arsenic and phosphorus implanted 〈100〉 silicon by rf sputtering titanium and forming the silicide using two‐step flash anneals at different temperatures. It is shown that the silicide sheet resistance is a sensitive function of the silicon surface condition prior to titanium sputtering; in particular, silicide films formed on heavily implanted silicon had significantly higher sheet resistance compared to films formed under identical conditions on lightly doped prime silicon. The higher silicide sheet resistance resulted because of the surface damage created during arsenic and phosphorus implantation and higher silicon dopant concentratio...

Selectively silicided vertical power double‐diffused metal–oxide semiconductor field effect transistors for high‐frequency power switching applications

A new power field effect transistor (FET) structure with selectively silicided gate and source regions is described. This structure simultaneously lowers the gate sheet resistance and source contact resistance. Vertical power double‐diffused metal‐oxide semiconductor field effect transistors fabricated using this technology have a specific on‐resistance of 0.53 mΩu2009cm2 for devices capable of blocking 50 V in the off‐state. Devices with cell density as high as 4 million cells/in.2 and die size as large as 200×220 mil have been successfully fabricated with excellent gate yield. These results represent the best ever reported forward conductivities for any type of power FET in the 50‐V reverse blocking range. Comparison of selectively silicided power FET’s with state of the art commercial nonsilicided FET’s indicates that the former have an order‐of‐magnitude lower gate sheet resistance, 8× smaller on‐resistance, and 2× smaller input capacitance.

Counterdoping of MOS channel (CDC)-a new technique of improving suppression of latching in insulated gate bipolar transistors

A novel technique of improving suppression of latching in insulated-gate bipolar transistors (IGBTs) is proposed and experimentally verified. By counterdoping the channel of the DMOS cell, the doping of the p-base can be increased up to a factor of two. Dynamic latching improvement of 40-80%, corresponding to the p-base doping increase, has been obtained. The degradation in forward blocking voltage was observed when the counterdoping dosage exceeds about 2*10/sup 12/ cm/sup -2/ for 600-V devices.<<ETX>>

Lateral insulated gate transistors with improved latching characteristics

Lateral insulated gate transistors were fabricated to study their applicability for power integrated circuits. Three independent techniques for improving latching current are described in this paper. We obtained devices that latch at 510 A/cm2, significantly greater than previously reported. We have also demonstrated devices that current-limit at 475 A/cm2without latching. Several device configurations are compared in terms of performance and processing trade-offs. In addition, computer simulations suggest a device design improvement that could result in a 30% increase in current density.