Zach Griffith

InP HBT IC Technology for Terahertz Frequencies: Fundamental Oscillators Up to 0.57 THz

We report on the development of a 0.25-μm InP HBT IC technology for lower end of the THz frequency band (0.3-3 THz). Transistors demonstrate an extrapolated fmax of >;800 GHz while maintaining a common-emitter breakdown voltage (BVCEO) >;4 V. The transistors have been integrated in a full IC process that includes three-levels of interconnects, and backside processing. The technology has been utilized for key circuit building blocks (amplifiers, oscillators, frequency dividers, PLL, etc), all operating at ≥300 GHz. Next, we report a series of fundamental oscillators operating up to 0.57 THz fabricated in a 0.25-μm InP HBT technology. Oscillator designs are based on a differential series-tuned topology followed by a common-base buffer, in a fixed-frequency or varactor-tuned scheme. For ≥400 GHz designs, a subharmonic down-conversion mixer is integrated to facilitate spectrum measurement. At optimum bias, the measured output power was -6.2, -5.6, and -19.2 dBm, for 310.2-, 412.9-, and 573.1-GHz designs, respectively, with PDC ≤ 115 mW. Varactor-tuned designs demonstrated 10.6-12.3 GHz of tuning bandwidth up to 300 GHz.

G-band (140-220 GHz) and W-band (75-110 GHz) InP DHBT medium power amplifiers

We report common-base medium power amplifiers designed for G-band (140-220 GHz) and W-band (75-110 GHz) in InP mesa double HBT technology. The common-base topology is preferred over common-emitter and common-collector topologies due to its superior high-frequency maximum stable gain (MSG). Base feed inductance and collector emitter overlap capacitance, however, reduce the common-base MSG. A single-sided collector contact reduces Cce and, hence, improves the MSG. A single-stage common-base tuned amplifier exhibited 7-dB small-signal gain at 176 GHz. This amplifier demonstrated 8.7-dBm output power with 5-dB associated power gain at 172 GHz. A two-stage common-base amplifier exhibited 8.1-dBm output power with 6.3-dB associated power gain at 176 GHz and demonstrated 9.1-dBm saturated output power. Another two-stage common-base amplifier exhibited 11.6-dBm output power with an associated power gain of 4.5 dB at 148 GHz. In the W-band, different designs of single-stage common-base power amplifiers demonstrated saturated output power of 15.1 dBm at 84 GHz and 13.7 dBm at 93 GHz

THz MMICs based on InP HBT Technology

An indium-phosphide (InP) double-heterojunction bipolar transistor (DHBT) based suite of terahertz monolithic integrated circuits (TMICs) fabricated using 256nm InP DHBT transistors and a multipurpose three metal layer interconnect system is reported. The InP DHBT MMIC process is well suited for TMICs due to its high bandwidth (fmax = 808 GHz) and high breakdown voltage (BVCBo = 4V) and integrated 10-µm thick layer of BCB dielectric supporting both low-loss THz microstrip lines for LNA, PA, and VCO tuning networks, and high-density thin-film interconnects for compact digital and analog blocks. TMIC low noise and driver amplifiers, fixed and voltage controlled oscillators, dynamic frequency dividers, and double-balanced Gilbert cell mixers have been designed and fabricated. These results demonstrate the capability of 256nm InP DHBT technology to enable sophisticated single-chip heterodyne receivers and exciters for operation at THz frequencies.

Highly integrated optical heterodyne phase-locked loop with phase/frequency detection.

A highly-integrated optical phase-locked loop with a phase/frequency detector and a single-sideband mixer (SSBM) has been proposed and demonstrated for the first time. A photonic integrated circuit (PIC) has been designed, fabricated and tested, together with an electronic IC (EIC). The PIC integrates a widely-tunable sampled-grating distributed-Bragg-reflector laser, an optical 90 degree hybrid and four high-speed photodetectors on the InGaAsP/InP platform. The EIC adds a single-sideband mixer, and a digital phase/frequency detector, to provide single-sideband heterodyne locking from -9 GHz to 7.5 GHz. The loop bandwith is 400 MHz.

Sub-300 nm InGaAs/InP Type-I DHBTs with a 150 nm collector, 30 nm base demonstrating 755 GHz f max and 416 GHz f T

We report InP/InGaAs/InP double heterojunction bipolar transistors (DHBT) fabricated using a simple mesa structure. The devices employ a 30 nm highly doped InGaAs base and a 150 nm InP collector containing an InGaAs/InAlAs superlattice grade. These devices exhibit a maximum f_max = 755 GHz with a 416 GHz /f_T. This is the highest f_max reported for a mesa HBT. Through the use of i-line lithography, the emitter junctions have been scaled from 500-600 nm down to 250-300 nm -all while maintaining similar collector to emitter area ratios. Because of the subsequent reduction to the base spreading resistance underneath the emitter R_b,spread and increased radial heat flow from the narrower junction, significant increases to f_max and reductions in device thermal resistance θ_JA are expected and observed. The HBT current gain β ≈ 24-35, BV_ceo = 4.60 V, BV_cbo = 5.34 V, and the devices operate up to 20 mW / μm² before self-heating is observed to affect the DC characteristics.

Low resistance, nonalloyed Ohmic contacts to InGaAs

We report extremely low specific contact resistivity (ρc) nonalloyed Ohmic contacts to n-type In0.53Ga0.47As, lattice matched to InP. Contacts were formed by oxidizing the semiconductor surface through exposure to ultraviolet-generated ozone, subsequently immersing the wafer in ammonium hydroxide (NH4OH, 14.8 normality), and finally depositing either Ti∕Pd∕Au contact metal by electron-beam evaporation or TiW contact metal by vacuum sputtering. Ti∕Pd∕Au contacts exhibited ρc of (0.73±0.44)Ωμm2—i.e., (7.3±4.4)×10−9Ωcm2—while TiW contacts exhibited ρc of (0.84±0.48)Ωμm2. The TiW contacts are thermally stable, showing no observable degradation in resistivity after a 500°C annealing of 1min duration.

InGaAs-InP DHBTs for increased digital IC bandwidth having a 391-GHz f/sub /spl tau// and 505-GHz f/sub max/

InP-In/sub 0.53/Ga/sub 0.47/As-InP double heterojunction bipolar transistors (DHBT) have been designed for use in high bandwidth digital and analog circuits, and fabricated using a conventional mesa structure. These devices exhibit a maximum 391-GHz f/sub /spl tau// and 505-GHz f/sub max/, which is the highest f/sub /spl tau// reported for an InP DHBT-as well as the highest simultaneous f/sub /spl tau// and f/sub max/ for any mesa HBT. The devices have been aggressively scaled laterally for reduced base-collector capacitance C/sub cb/. In addition, the base sheet resistance /spl rho//sub s/ along with the base and emitter contact resistivities /spl rho//sub c/ have been lowered. The dc current gain /spl beta/ is /spl ap/36 and V/sub BR,CEO/=5.1 V. The devices reported here employ a 30-nm highly doped InGaAs base, and a 150-nm collector containing an InGaAs-InAlAs superlattice grade at the base-collector junction. From this device design we also report a 142-GHz static frequency divider (a digital figure of merit for a device technology) fabricated on the same wafer. The divider operation is fully static, operating from f/sub clk/=3 to 142.0 GHz while dissipating /spl ap/800 mW of power in the circuit core. The circuit employs single-buffered emitter coupled logic (ECL) and inductive peaking. A microstrip wiring environment is employed for high interconnect density, and to minimize loss and impedance mismatch at frequencies >100 GHz.

Transistor and circuit design for 100-200 GHz ICs

Compared to SiGe, InP HBTs offer superior electron transport properties but inferior scaling and parasitic reduction. Figures of merit for mixed-signal ICs are developed and HBT scaling laws introduced. Device and circuit results are summarized, including a simultaneous 450 GHz f/sub /spl tau// and 490 GHz f/sub max/ DHBT, 172-GHz amplifiers with 8.3-dBm output power and 4.5-dB associated power gain, and 150-GHz static frequency dividers (a digital circuit figure-of-merit for a device technology). To compete with advanced 100-nm SiGe processes, InP HBTs must be similarly scaled and high process yields are imperative. Described are several process modules in development: these include an emitter-base dielectric sidewall spacer for increased yield, a collector pedestal implant for reduced extrinsic C/sub cb/, and emitter junction regrowth for reduced base and emitter resistances.

InGaAs/InP DHBTs with 120-nm collector having simultaneously high f/sub /spl tau//, f/sub max//spl ges/450 GHz

InP/In/sub 0.53/Ga/sub 0.47/As/InP double heterojunction bipolar transistors (DHBT) have been designed for increased bandwidth digital and analog circuits, and fabricated using a conventional mesa structure. These devices exhibit a maximum 450 GHz f/sub /spl tau// and 490 GHz f/sub max/, which is the highest simultaneous f/sub /spl tau// and f/sub max/ for any HBT. The devices have been scaled vertically for reduced electron collector transit time and aggressively scaled laterally to minimize the base-collector capacitance associated with thinner collectors. The dc current gain /spl beta/ is /spl ap/ 40 and V/sub BR,CEO/=3.9 V. The devices operate up to 25 mW//spl mu/m/sup 2/ dissipation (failing at J/sub e/=10 mA//spl mu/m/sup 2/, V/sub ce/=2.5 V, /spl Delta/T/sub failure/=301 K) and there is no evidence of current blocking up to J/sub e//spl ges/12 mA//spl mu/m/sup 2/ at V/sub ce/=2.0 V from the base-collector grade. The devices reported here employ a 30-nm highly doped InGaAs base, and a 120-nm collector containing an InGaAs/InAlAs superlattice grade at the base-collector junction.

InGaAs-InP mesa DHBTs with simultaneously high f/sub /spl tau// and f/sub max/ and low C/sub cb//I/sub c/ ratio

We report an InP-InGaAs-InP double heterojunction bipolar transistor (DHBT), fabricated using a conventional triple mesa structure, exhibiting a 370-GHz f/sub /spl tau// and 459-GHz f/sub max/, which is to our knowledge the highest f/sub /spl tau// reported for a mesa InP DHBT-as well as the highest simultaneous f/sub /spl tau// and f/sub max/ for any mesa HBT. The collector semiconductor was undercut to reduce the base-collector capacitance, producing a C/sub cb//I/sub c/ ratio of 0.28 ps/V at V/sub cb/=0.5 V. The V/sub BR,CEO/ is 5.6 V and the devices fail thermally only at >18 mW//spl mu/m/sup 2/, allowing dc bias from J/sub e/=4.8 mA//spl mu/m/sup 2/ at V/sub ce/=3.9 V to J/sub e/=12.5 mA//spl mu/m/sup 2/ at V/sub ce/=1.5 V. The device employs a 30 nm carbon-doped InGaAs base with graded base doping, and an InGaAs-InAlAs superlattice grade in the base-collector junction that contributes to a total depleted collector thickness of 150 nm.