Petrus Hubertus Cornelis Magnee

Record power added efficiency of bipolar power transistors for low voltage wireless applications

To increase the power added efficiency (PAE) of low voltage RF bipolar power transistors for cellular applications, we investigated the influence of transistor parasitics on PAE. We found that reducing the output capacitance increases the PAE due to better second harmonic tuning. By optimizing the transistor for a low output capacitance we achieved a record PAE of 71% at 0.5 Watt, 1.8 GHz and 3.5 V supply voltage.

Enhanced RF power gain by eliminating the emitter bondwire inductance in emitter plug grounded mounted bipolar transistors

For the first time, we show an enhanced RF power gain by eliminating the emitter bondwire inductance in emitter plug grounded mounted bipolar transistors. By grounding the emitter with a substrate contact to a low-ohmic substrate, the emitter bondwire is effectively short-circuited. At maximum output power, 0.5 W with a power added efficiency >60%, an increase in power gain of 2 dB, up to 14.5 dB, is observed. For 0.2 W output power, an increase of 5 dB, up to 19 dB, is observed.

High performance SiGeC HBT integrated into a 0.25 /spl mu/m BiCMOS technology featuring record 88% power-added efficiency

This paper reports on the power performance of RF high-breakdown voltage (>16.5 V) SiGeC HBT power devices, which have been successfully integrated into a BiCMOS platform featuring 0.25 /spl mu/m CMOS and a full set of high-quality passives. These devices have an excellent tradeoff between power gain and breakdown voltage. The high speed combined with low parasitic elements enables over 80% power-added efficiency (PAE) and corresponding power gains (G/sub p/) of 18 dB and higher over a relatively wide range of power densities. A peak performance of 88% PAE and 20 dB G/sub p/ is obtained at 0.25 W continuous-wave output power with a 792 /spl mu/m emitter length device (396 /spl mu/m/sup 2/ emitter area) operating at 1.8 GHz with 3.3 V supply voltage. Excellent power scaling versus emitter area is obtained. Measured output power shows an ideal increase of 3 dB when doubling the area. Also the corresponding matching scales. This is achieved by minimizing parasitic elements using deep trench isolation and careful design of the metal wiring. Furthermore, the base and emitter doping profiles are tuned to minimize the temperature dependence of the power gain. In combination with the high PAE, no effect of self-heating on power scaling is found.

The influence of parasitic resistances on the f/sub T/-optimisation of high-speed SiGe-HBTs

We study the influence of parasitic series resistances on the cut-off frequency of high-speed SiGe hetero-junction bipolar transistors. Due to coupling of the parasitic resistances with the internal collector-base capacitance, significant extra delay time is introduced. This extra delay will cause saturation, or even a decrease of f/sub T/ at higher collector doping levels. In addition, we study the optimisation of an n-cap emitter profile, which is only possible when the collector delay is reduced to a minimum, and the series resistances are properly included.

On-glass process option for BiCMOS technology

An industrial SiGe BiCMOS technology is presented, in which the silicon substrate has been removed and replaced by a lossless glass substrate. This will enable the integration of better passives, while the active devices remain fully library compatible. Specifically, ideal NPN characteristics with 111/94 GHz f/sub T//f/sub max/ are shown without significant degradation of the thermal characteristics. This substrate transfer technology requires almost no changes to the standard processing and gives access to high-performance inverse NPN and vertical PNP devices, in addition to the lossless substrate.