Petteri Litmanen

A direct-conversion receiver for the 3G WCDMA standard

A highly integrated direct-conversion receiver that satisfies requirements of the third-generation wide-band code-division multiple-access mobile phone standard is described. The receiver integrated circuit includes the front-end low-noise amplifier, downconversion mixers, baseband variable-gain amplifiers, channel-select filters, and the frequency synthesizer. External components are limited to matching elements required for the low-noise amplifier and the mixers and two passive band-select filters. The receiver is implemented in a SiGe BiCMOS process and consumes a total current of 46 mA from a 2.7-V supply.

Analog Path for Triple Band WCDMA Polar Modulated Transmitter in 90nm CMOS

We present a fully integrated analog path for a 3 G polar transmitter in 90 nm CMOS. It includes a quad band Digitally Controlled Oscillator providing modulation for the phase data and a single stage Digital Pre-Power Amplifier that combines the phase and amplitude signals while providing the dynamic range for WCDMA. The chip, with integrated LDOs, consumes 60 mA from a 1.4 V supply while providing 11 dBm CW power at 1950 MHz, 87 dB dynamic range without any calibration, and PN of -157 dBc/Hz at 40 MHz.

Quad Band Digitally Controlled Oscillator for WCDMA Transmitter in 90nm CMOS

We present the first published implementation and measurements of a fully integrated phase path for a 3G polar transmitter in deep sub micron CMOS. It includes a single quad band digitally controlled oscillator (DCO) providing modulation capability to handle the wide bandwidth of the WCDMA phase (frequency) data and a switched inverter divider. The complete chip, with integrated LDOs, consumes 20mA from a 1.4V supply while providing a PN of -157dBc/Hz at a 40MHz offset for a 2GHz output

A direct conversion receiver for the 3G WCDMA standard

A highly integrated direct-conversion receiver that satisfies requirements of the third generation Wideband Code Division Multiple Access (WCDMA) mobile phone standard is described. The receiver IC includes the front-end low-noise amplifier, down-conversion mixers, channel select filters, baseband variable gain amplifiers, and the entire frequency synthesizer, including the voltage controlled oscillator, buffers and phase-locked loop.

9.1 A 45nm CMOS RF-to-Bits LTE/WCDMA FDD/TDD 2×2 MIMO base-station transceiver SoC with 200MHz RF bandwidth

Increasing mobile data demands are pushing cellular network capacity. Massive MIMO base stations with large antenna arrays and smaller cell sizes demand higher integration in radio transceivers than what is available [1].

A high magnetic coupling, low loss, stacked balun in digital 65nm CMOS

We present a high magnetic coupling, low loss, stacked balun using a thick aluminum bonding metal layer over a thick copper layer. The thick copper is used to realize a differential primary input winding that resides directly underneath a single ended spiral winding using the aluminum. The spiral forms the single ended secondary output of the balun and is rotated by 90° so as to prevent any metal shorting for its cross under. Occupying an area of 0.078mm2 on a digital 65nm process, a 5 turn primary with a 3 turn secondary has a measured coupling of 0.94 and a total balun loss of 1.55dB at 1845MHz.

Silicon-package co-design of a 45nm 200MHz bandwidth CMOS RF-to-Serdes transceiver system on chip (SoC)

In this paper we detail the silicon-package electrical co-design of a 45nm CMOS, 400MHz to 4GHz, 3GPP TDD & FDD, RF-to-Serdes base station transceiver system on chip (SoC). Electrical optimization of the silicon-package RF paths, to achieve desired performance, was achieved through a coupled circuit-to-electromagnetic co-design modeling and simulation flow. Laboratory measurements, on a real SoC system, are presented that validate the integrity of the modeling and simulation methodology.