Siraj Akhtar

Analog Path for Triple Band WCDMA Polar Modulated Transmitter in 90nm CMOS

We present a fully integrated analog path for a 3 G polar transmitter in 90 nm CMOS. It includes a quad band Digitally Controlled Oscillator providing modulation for the phase data and a single stage Digital Pre-Power Amplifier that combines the phase and amplitude signals while providing the dynamic range for WCDMA. The chip, with integrated LDOs, consumes 60 mA from a 1.4 V supply while providing 11 dBm CW power at 1950 MHz, 87 dB dynamic range without any calibration, and PN of -157 dBc/Hz at 40 MHz.

Quad Band Digitally Controlled Oscillator for WCDMA Transmitter in 90nm CMOS

We present the first published implementation and measurements of a fully integrated phase path for a 3G polar transmitter in deep sub micron CMOS. It includes a single quad band digitally controlled oscillator (DCO) providing modulation capability to handle the wide bandwidth of the WCDMA phase (frequency) data and a switched inverter divider. The complete chip, with integrated LDOs, consumes 20mA from a 1.4V supply while providing a PN of -157dBc/Hz at a 40MHz offset for a 2GHz output

Impact of transistor reliability on RF oscillator phase noise degradation

The impact of deep sub-micron CMOS transistor reliability on RF oscillator phase noise degradation is demonstrated along with the importance of off-state drain stress for large signal RF applications. Process and device optimization was successful in reducing phase noise degradation to acceptable levels.

9.1 A 45nm CMOS RF-to-Bits LTE/WCDMA FDD/TDD 2×2 MIMO base-station transceiver SoC with 200MHz RF bandwidth

Increasing mobile data demands are pushing cellular network capacity. Massive MIMO base stations with large antenna arrays and smaller cell sizes demand higher integration in radio transceivers than what is available [1].

Phase Noise Reduction in High Speed Frequency Divider

Maximum operating frequency, phase noise characteristics close to output carrier frequency and power consumption during operation are major parameters of a frequency divider. Since these parameters are interrelated, design optimization involves tradeoffs among them. A new differential D-latch based topology for a low phase noise frequency divider for cellular transceivers is presented. An optimization process for the design of frequency divider is given and various phenomena that dominate phase noise and high frequency behavior of the frequency dividers are discussed. The proposed divider designed using 65 nm CMOS has a maximum input frequency of 11.8 GHz with phase noise level of 153.3 dBc/Hz at an offset of 20 MHz. It consumes 11 mA average current while operating at a nominal frequency of 8 GHz

A high magnetic coupling, low loss, stacked balun in digital 65nm CMOS

We present a high magnetic coupling, low loss, stacked balun using a thick aluminum bonding metal layer over a thick copper layer. The thick copper is used to realize a differential primary input winding that resides directly underneath a single ended spiral winding using the aluminum. The spiral forms the single ended secondary output of the balun and is rotated by 90° so as to prevent any metal shorting for its cross under. Occupying an area of 0.078mm2 on a digital 65nm process, a 5 turn primary with a 3 turn secondary has a measured coupling of 0.94 and a total balun loss of 1.55dB at 1845MHz.

Silicon-package co-design of a 45nm 200MHz bandwidth CMOS RF-to-Serdes transceiver system on chip (SoC)

In this paper we detail the silicon-package electrical co-design of a 45nm CMOS, 400MHz to 4GHz, 3GPP TDD & FDD, RF-to-Serdes base station transceiver system on chip (SoC). Electrical optimization of the silicon-package RF paths, to achieve desired performance, was achieved through a coupled circuit-to-electromagnetic co-design modeling and simulation flow. Laboratory measurements, on a real SoC system, are presented that validate the integrity of the modeling and simulation methodology.

A 28mW WCDMA/GSM/GPRS/EDGE transformer-based receiver in 45nm CMOS

A transformer-based receiver designed in 45nm CMOS that meets WCDMA, GSM, GPRS, and EDGE system requirements is presented. The receiver requires no interstage SAW filters and consumes 20mA from 1.4V. The use of a transformer at the LNA output helps achieve high linearity by lowering the voltage swing while simultaneously providing current gain. The analog back end is implemented with two cascaded gain stages and a 2nd order ΣΔ ADC. The receiver has a gain of 60dB, noise figure of 3.0dB and an IIP2 of ≫+50dBm on both I+Q channels. The die area is 1.35mm2 for 4 bands.