Ph. Galy

ESD RF protections in advanced CMOS technologies and its parasitic capacitance evaluation

Electrostatic Discharge (ESD) protection for advanced CMOS technologies is a challenge due to down-scaling which introduces a reduction of the intrinsic robustness. Moreover, another challenge is the RF ESD protection in analogue IO pad. Thus, when you merge both topics the challenges are major. This paper shows a methodology, tools and silicon measurements of ESD RF parasitic capacitance in C65nm & C45nm to reach 10Ghz & 20Ghz bandwidth for 1kV & 2kV HBM.

BIMOS transistor in thin silicon film and new solutions for ESD protection in FDSOI UTBB CMOS technology

The purpose of this study is to evaluate the ESD protection behavior using BIMOS transistors integrated in ultrathin silicon film for 28 nm FDSOI UTBB high-k metal gate technology. Using as a reference our measurements in hybrid bulk structures we extend the BIMOS design towards the ultrathin silicon film. Evaluations are done based on 3D TCAD simulation with standard physical models using ACS method and quasi-static DC stress (AVS method).

ESD protection with BIMOS transistor for bulk & FDSOI advanced CMOS technology

The purpose of this paper is to introduce the ESD protection using BIMOS transistor in bulk CMOS and in hybrid area for 28nm FDSOI High k metal gate. Moreover the DC behavior is also performed. Thus, this study introduces an ESD protection with a minimum of silicon area consumption and efficient to protect the MOS transistors with thin & thick oxide and also in thin silicon film. TCAD simulations are done in 2D and 3D with classical equation of semiconductor. Moreover, all results are done through silicon measurements on demonstrator devices.

GDNMOS: A new high voltage device for ESD protection in 28nm UTBB FD-SOI technology

We propose a novel device (GDNMOS: Gated Diode merged NMOS) fabricated with 28nm UTBB FD-SOI high-k metal gate technology. Variable electrostatic doping (gate-induced) in diode and transistor body enables reconfigurable operation, in particular in thyristor mode. This innovative architecture demonstrates excellent capability for high-voltage protection while maintaining a latch-up free behavior.

Competitive 1T-DRAM in 28 nm FDSOI technology for low-power embedded memory

We demonstrate experimentally a capacitorless IT-DRAM fabricated with 28 nm FDSOI. The Z2-FET memory cell features a large current sense margin and long retention time at T = 25°C and 85°C. Systematic measurements show that Z2-FET exhibits negligible OFF-state current at low drain/gate bias and is suitable as a low-power embedded memory.

New BIMOS transistor in 28nm FDSOI technology: Operation in 4-Gate JFET mode

In this paper, we introduce a new BIMOS transistor fabricated with 28nm high-k metal-gate FDSOI UTBB technology. The device is highly flexible and reconfigurable as it can be operated in MOS, Bipolar, Hybrid and 4-Gate modes. We investigate the bias conditions for JFET-like operation and show promising performance even in structures with ultrathin Si film.

Electro Static Discharge (ESD) one real life event: Physical impact and protection challenges in advanced CMOS technologies

The main purpose of this paper is to give an overview of Electro-Static Discharge (ESD) event with its impacts on advanced CMOS technologies. Afterwards, a discussion will be on ESD elementary devices and how to provide an efficient ESD network protection for System On Chip (SOC). These solutions are obtained according to the ESD window of the planar technology on bulk or Fully Depleted (FD) SOI. Thus it will be possible to imagine what could be the next challenges for an ESD protection.

The mystery of the Z2-FET 1T-DRAM memory

We review the operation mechanisms of the Z2-FET underlining its attractiveness as a capacitorless DRAM memory. The main parameters that govern the memory performance are discussed based on systematic experiments and simulations.