Philip J. Kuekes

'Memristive' switches enable 'stateful' logic operations via material implication.

The authors of the International Technology Roadmap for Semiconductors—the industry consensus set of goals established for advancing silicon integrated circuit technology—have challenged the computing research community to find new physical state variables (other than charge or voltage), new devices, and new architectures that offer memory and logic functions beyond those available with standard transistors. Recently, ultra-dense resistive memory arrays built from various two-terminal semiconductor or insulator thin film devices have been demonstrated. Among these, bipolar voltage-actuated switches have been identified as physical realizations of ‘memristors’ or memristive devices, combining the electrical properties of a memory element and a resistor. Such devices were first hypothesized by Chua in 1971 (ref. 15), and are characterized by one or more state variables that define the resistance of the switch depending upon its voltage history. Here we show that this family of nonlinear dynamical memory devices can also be used for logic operations: we demonstrate that they can execute material implication (IMP), which is a fundamental Boolean logic operation on two variables p and q such that pIMPq is equivalent to (NOTp)ORq. Incorporated within an appropriate circuit, memristive switches can thus perform ‘stateful’ logic operations for which the same devices serve simultaneously as gates (logic) and latches (memory) that use resistance instead of voltage or charge as the physical state variable.

Writing to and reading from a nano-scale crossbar memory based on memristors

We present a design study for a nano-scale crossbar memory system that uses memristors with symmetrical but highly nonlinear current-voltage characteristics as memory elements. The memory is non-volatile since the memristors retain their state when un-powered. In order to address the nano-wires that make up this nano-scale crossbar, we use two coded demultiplexers implemented using mixed-scale crossbars (in which CMOS-wires cross nano-wires and in which the crosspoint junctions have one-time configurable memristors). This memory system does not utilize the kind of devices (diodes or transistors) that are normally used to isolate the memory cell being written to and read from in conventional memories. Instead, special techniques are introduced to perform the writing and the reading operation reliably by taking advantage of the nonlinearity of the type of memristors used. After discussing both writing and reading strategies for our memory system in general, we focus on a 64 x 64 memory array and present simulation results that show the feasibility of these writing and reading procedures. Besides simulating the case where all device parameters assume exactly their nominal value, we also simulate the much more realistic case where the device parameters stray around their nominal value: we observe a degradation in margins, but writing and reading is still feasible. These simulation results are based on a device model for memristors derived from measurements of fabricated devices in nano-scale crossbars using Pt and Ti nano-wires and using oxygen-depleted TiO(2) as the switching material.

CMOS-like logic in defective, nanoscale crossbars

We present an approach to building defect-tolerant, nanoscale compute fabrics out of assemblies of defective crossbars of configurable FETs and switches. The simplest structure, the complementary/symmetry array, can implement AND-OR-INVERT functions, which are powerful enough to implement general computation. These arrays can be combined to create logic blocks capable of implementing sum-of-product functions, and still larger computations, such as state machines, can be obtained by adding additional routing blocks. We demonstrate the defect tolerance of such structures through experimental studies of the compilation of a small microprocessor onto a crossbar fabric with varying defect rates and compiler mapping parameters.

The crossbar latch: Logic value storage, restoration, and inversion in crossbar circuits

Programmable crossbar circuits are one key architecture proposed for integrated nanoscale electronics. Emphasizing practicality of fabrication, many scenarios advocate crossbar circuits based on two-terminal devices. In this case, however, signal restoration and inversion remain critical weaknesses. Restoration is essential before the degraded output of one logic gate can drive the input of a subsequent logic gate. Inversion is required to generate a complete logic family. Here we describe and demonstrate a solution to both problems, the crossbar latch. This device stores a logic value on a signal wire, enabling logic value restoration, and inversion. In combination with resistor/diode logic gates, these operations in principle enable universal computing for crossbar circuits, and potentially, integrated nanoscale electronics.

Defect tolerance on the Teramac custom computer

Teramac is a large custom computer which works correctly despite the fact that three quarters of its FPGAs contain defects. This is accomplished through unprecedented use of defect tolerance, which substantially reduces Teramacs cost and permits it to have an unusually complex interconnection network. Teramac tolerates defective resources, like gates and wires, that are introduced during the manufacture of its FPGAs and other components, and during assembly of the system. We have developed methods to precisely locate defects. User designs are mapped onto the system by a completely automated process that avoids the defects and hides the defect tolerance from the user. Defective components are not physically removed from the system.

Diffusion of Adhesion Layer Metals Controls Nanoscale Memristive Switching

First prominent more than 40 years ago, [ 1 ] electrical resistance switching in conductor/insulator/conductor structures has regained signifi cant attention in the last decade, [ 2–16 ] motivated by the search for alternatives to conventional semiconductor electronics. [ 17 ] Recent results have shown promising device behaviors, such as reversible, non-volatile, fast ( < 10 ns), lowpower ( ∼ 1 pJ/operation) and multiple-state switching, [ 18–26 ]

Defect-tolerant interconnect to nanoelectronic circuits: internally redundant demultiplexers based on error-correcting codes

We describe a family of defect-tolerant demultiplexers based on error-correcting codes. A conventional demultiplexer with a k-bit input address and 2k-bit output may be fortified against certain defect types by widening its address bus to n>k bits to permit an encoded address to be used within the demultiplexer. The redundant address is computed by an encoder that guarantees a minimum Hamming distance d between addresses, which sparsely populate an expanded address space. The increased Hamming distances between addresses are especially tolerant of stuck-open defects (and broken wires, which are equivalent to multiple stuck-open defects). For each address width k, there are a series of demultiplexer designs with increasing internal redundancy, increasing d, and increasing capability for defect tolerance. These circuit designs are especially suitable for nano-scale crossbars; in particular, they may be realized at the interface where the CMOS wires of conventional microelectronics cross nano-wires to form a mixed-scale interconnect crossbar. Thus, a small number (2n) of CMOS wires may be used to control a much larger number (2k) of nano-wires; the family of encoded demultiplexer designs provides a robust interface to the nano-circuitry, giving significant protection from manufacturing mistakes at the cost of a relatively small amount of area overhead . This is a qualitatively new application of error-correcting codes, the analysis of which combines elements of the conventional coding-theoretic notions of full-error and erasure correction. In particular, a code with minimum distance d guarantees tolerance to up to d−1 defects per nano-wire, in analogy to conventional erasure correction.

Radiation Hardness of

Semiconducting TiO2 displays non-volatile multi-state, hysteretic behavior in its I-V characteristics that can be exploited as a memory material in a memristive device. We exposed memristive TiO2 devices in the on and off resistance states to 45 Mrad(Si) of ~1-MeV gamma radiation and 23 Mrad(Si) of 941-MeV Bi-ions under zero bias conditions and none of the devices were degraded. These results suggest that TiO2 memristive devices are good candidates for radiation hard electronics for aerospace.

{\rm TiO}_{2}

The voltage margin of a resistor-logic demultiplexer can be improved significantly by basing its connection pattern on a constant-weight code. Each distinct code determines a unique demultiplexer, and therefore a large family of circuits is defined. We consider using these demultiplexers for building nanoscale crossbar memories, and determine the voltage margin of the memory system based on a particular code. We determine a purely code-theoretic criterion for selecting codes that will yield memories with large voltage margins, which is to minimize the ratio of the maximum to the minimum Hamming distance between distinct codewords. For the specific example of a 64 × 64 crossbar, we discuss what codes provide optimal performance for a memory.

Memristive Junctions

Molecular electronics are difficult to fabricate with precise positioning of large numbers of devices and their connections. Self-assembly techniques can create such circuits but with some random variation in their connection locations and characteristics. Using simulations, we show how to produce reliable circuits in spite of this variation by adding enough redundant components to pass a sharp threshold in likely circuit correctness. As an example of this approach, we examine a demultiplexer circuit, which is useful for connecting nanoscale circuits with larger conventional circuits.