Duncan Stewart

'Memristive' switches enable 'stateful' logic operations via material implication.

The authors of the International Technology Roadmap for Semiconductors—the industry consensus set of goals established for advancing silicon integrated circuit technology—have challenged the computing research community to find new physical state variables (other than charge or voltage), new devices, and new architectures that offer memory and logic functions beyond those available with standard transistors. Recently, ultra-dense resistive memory arrays built from various two-terminal semiconductor or insulator thin film devices have been demonstrated. Among these, bipolar voltage-actuated switches have been identified as physical realizations of ‘memristors’ or memristive devices, combining the electrical properties of a memory element and a resistor. Such devices were first hypothesized by Chua in 1971 (ref. 15), and are characterized by one or more state variables that define the resistance of the switch depending upon its voltage history. Here we show that this family of nonlinear dynamical memory devices can also be used for logic operations: we demonstrate that they can execute material implication (IMP), which is a fundamental Boolean logic operation on two variables p and q such that pIMPq is equivalent to (NOTp)ORq. Incorporated within an appropriate circuit, memristive switches can thus perform ‘stateful’ logic operations for which the same devices serve simultaneously as gates (logic) and latches (memory) that use resistance instead of voltage or charge as the physical state variable.

Writing to and reading from a nano-scale crossbar memory based on memristors

We present a design study for a nano-scale crossbar memory system that uses memristors with symmetrical but highly nonlinear current-voltage characteristics as memory elements. The memory is non-volatile since the memristors retain their state when un-powered. In order to address the nano-wires that make up this nano-scale crossbar, we use two coded demultiplexers implemented using mixed-scale crossbars (in which CMOS-wires cross nano-wires and in which the crosspoint junctions have one-time configurable memristors). This memory system does not utilize the kind of devices (diodes or transistors) that are normally used to isolate the memory cell being written to and read from in conventional memories. Instead, special techniques are introduced to perform the writing and the reading operation reliably by taking advantage of the nonlinearity of the type of memristors used. After discussing both writing and reading strategies for our memory system in general, we focus on a 64 x 64 memory array and present simulation results that show the feasibility of these writing and reading procedures. Besides simulating the case where all device parameters assume exactly their nominal value, we also simulate the much more realistic case where the device parameters stray around their nominal value: we observe a degradation in margins, but writing and reading is still feasible. These simulation results are based on a device model for memristors derived from measurements of fabricated devices in nano-scale crossbars using Pt and Ti nano-wires and using oxygen-depleted TiO(2) as the switching material.

Hybrid CMOS/memristor circuits

This is a brief review of recent work on the prospective hybrid CMOS/memristor circuits. Such hybrids combine the flexibility, reliability and high functionality of the CMOS subsystem with very high density of nanoscale thin film resistance switching devices operating on different physical principles. Simulation and initial experimental results demonstrate that performance of CMOS/memristor circuits for several important applications is well beyond scaling limits of conventional VLSI paradigm.

High integrity metal/organic device interfaces via low temperature buffer layer assisted metal atom nucleation

The ability to generate sharp, high integrity metal/organic film interfaces is demonstrated by the use of a buffer layer of Xe condensate during the vapor deposition of Au atoms onto a CH3(CH2)11S-/Au{111} self-assembled monolayer (SAM), a normally highly permeable film for the metal atoms in spite of the high degree of molecular organization and ordering. Atomic force microscopy conductance and topographic imaging reveals the intervening buffer can result in complete elimination of typical electrically shorting metal filaments and metal atom penetration into the SAM over large area contacts. This deposition method provides a highly reproducible way to form high integrity top metal contacts for demanding applications such as molecular electronic devices.

Origin of inverse tunneling magnetoresistance in a symmetric junction revealed by delaminating the buried electronic interface

Electrical properties of modern electronic devices are usually controlled by the physical and chemical structure of one or more buried material interfaces. Accessing these buried interfaces by energetic ion milling can destroy this structural information. We report a delamination technique that exposes pristine buried interfaces for x-ray photoemission spectroscopy. We use this technique to show that unusual inverse tunneling magnetoresistance in a nominally symmetric (Co,Fe)/AlOx/(Co,Fe) magnetic tunnel junction devices is attributable to subtle over-oxidation of the lower AlOx/CoFe interface. Ion-milling investigation of the same samples misleads by chemically reducing the signature Fe oxide species during milling.