Philipp Kulse

InP-DHBT-on-BiCMOS Technology With

This paper presents a novel InP-SiGe BiCMOS technology using wafer-scale heterogeneous integration. The vertical stacking of the InP double heterojunction bipolar transistor (DHBT) circuitry directly on top of the BiCMOS wafer enables ultra-broadband interconnects with <; 0.2 dB insertion loss from 0-100 GHz. The 0.8 × 5 μm2 InP DHBTs show fT/fmax of 400/350 GHz with an output power of more than 26 mW at 96 GHz. These are record values for a heterogeneously integrated transistor on silicon. As a circuit example, a 164-GHz signal source is presented. It features a voltage-controlled oscillator in BiCMOS, which drives a doubler-amplifier chain in InP DHBT technology.

f_{T}/f_{\max}

In this paper, a fully BiCMOS integrated microfluidic platform for bio-MEMS applications is demonstrated. The novel integration process flow provides very flexible size of micro-channels in BiCMOS chip and brings the fluid very close to the sensors. The platform is demonstrated with BiCMOS integrated 120 GHz dielectric sensor and the changes of the dielectric constant of different fluids in the channel are successfully detected. The high reproducibility, small size, high throughput and low-cost process make the presented BiCMOS integrated microfluidic channel technology as a key platform for bio-MEMS and THz-sensing applications.

of 400/350 GHz for Heterogeneous Integrated Millimeter-Wave Sources

In this work, the development of engineered silicon substrates for a novel via-middle TSV integration concept is demonstrated. These substrates include 3D buried etch-stop layers which provide both an ideal vertical and lateral etch-stop for TSV trench etching thus enabling the simultaneous realization of different size of TSVs on the same silicon substrate. Beside standard BiCMOS and TSV fabrication steps, only a low-temperature fusion bonding process is applied and the integration concept is realized without adding an additional mask to the established BiCMOS via-middle TSV technology. As a result, the developed technique is very promising to realize different dimensions of TSVs on the same substrate for future smart system applications.

BiCMOS integrated microfluidic platform for Bio-MEMS applications

In the last decades the semiconductor technology has been driven by Moore’s law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules additionally require to process the backside of the wafer; thus require an accurate alignment between the front and backside of the wafer. In previous work an advanced back to front side alignment technique and implementation into IHP’s 0.25/0.13 µm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8-9]. In this work, the non-contact infrared alignment system of the Nikon® i-line Stepper NSR-SF150 for both alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the offsets between all different FIA’s into account, after correcting the wafer rotation induced FIA position errors, hence an overlay for the stacked wafers can be determined. The developed approach has been validated by a standard front side resist in resist experiment. After the successful validation of the developed technique, special wafer stacks with FIA alignment marks in the bonding interface are fabricated and exposed. Following overlay calculation shows an overlay of less than 200 nm, which enables very accurate process condition for highly scaled TSV integration and advanced substrate integration into IHP’s 0.25/0.13 µm SiGe:C BiCMOS technology. The developed technique also allows using significantly smaller alignment marks (i.e. standard FIA alignment marks). Furthermore, the presented method is used, in case of wafer bow related overlay tool problems, for the overlay evaluation of the last two metal layers from production wafers prepared in IHP’s standard 0.25/0.13 µm SiGe:C BiCMOS technology. In conclusion, the exposure and measurement job can be done with the same tool, minimizing the back to front side/interface top layer misalignment which leads to a significant device performance improvement of backside/TSV integrated components and technologies.

Accurate Depth Control of Through-Silicon Vias by Substrate Integrated Etch Stop Layers

The state-of-the-art microbolometers are mainly based on polycrystalline or amorphous materials, typically Vanadium oxide (VOx) or amorphous-Silicon (a-Si), which only have modest temperature sensitivities and noise characteristics. The properties of single crystalline SiGe/Si multi quantum wells (MQWs) have been proposed as a promising material1. Particularly, SiGe/Si MQWs structure with high Ge concentration is expected to provide very high temperature coefficient of resistance (TCR) values between 6 to 8% 2. Although SiGe/Si MQWs structure as a thermistor material is extremely promising, difficulty of defect free deposition and high sheet resistance of high Ge concentrated SiGe layers are the two main bottlenecks of this approach. In this work, a very high TCR of -5.5 %/K is achieved for SiGe/Si MQWs including 50% Ge with an acceptable noise value of 2.7 x 10-13 V2/Hz at 10 Hz. The initial pixel resistance of 3 period of SiGe/Si MQWs with 50% Ge concentration is measured as 21 MΩ, which might not be compatible with the ROIC design. By the optimization of insitu Boron (B) doping level in SiGe layers of the MQW stack, 210 kΩ for 25 x 25 μm2 pixel size is achieved. The optimized B doping density of ~1 x 1018 cm-3 in SiGe wells did not cause any significant change in the TCR value whereas the 1/f noise performance is even enhanced due to the in-situ doping process and measured as 2.9 x 10-14 V2/Hz at 10 Hz.

I-line stepper based overlay evaluation method for wafer bonding applications

In the last decades the semiconductor technology has been driven by Moore’s law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules require addition backside processing of the wafer; thus an accurate alignment between the front and backside of the wafer is mandatory. In previous work an advanced back to front side alignment technique and implementation into IHP’s 0.25/0.13 μm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8]. Therefore, the available overlay measurement techniques are not suitable if overlay and alignment marks are realized at the bonding interface of a wafer stack which consists of both a silicon device and a silicon carrier wafer. The former used EVG 40NT automated overlay measurement system, which use two opposite positioned microscopes inspecting simultaneous the wafer back and front side, is not capable measuring embedded overlay marks. In this work, the non-contact infrared alignment system of the Nikon i-line Stepper NSR-SF150 for both the alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the offsets between all different FIA’s into account, after correcting the wafer rotation induced FIA position errors, hence an overlay for the stacked wafers can be determined. The developed approach has been validated by a standard back to front side application. The overlay was measured and determined using both, the EVG NT40 automated measurement system with special overlay marks and the measurement of the FIA marks of the front and back side layer. A comparison of both results shows mismatches in x and y translations smaller than 200 nm, which is relatively small compared to the overlay tolerances of ±500 nm for the back to front side process. After the successful validation of the developed technique, special wafer stacks with FIA alignment marks in the bonding interface are fabricated. Due to the super IR light transparency of both doubled side polished wafers, the embedded FIA marks generate a stable and clear signal for accurate x and y wafer coordinate positioning. The FIA marks of the device wafer top layer were measured under standard condition in a developed photoresist mask without IR illumination. Following overlay calculation shows an overlay of less than 200 nm, which enables very accurate process condition for highly scaled TSV integration and advanced substrate integration into IHP’s 0.25/0.13 μm SiGe:C BiCMOS technology. The presented method can be applied for both the standard back to front side process technologies and also new temporary and permanent wafer bonding applications.