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Dive into the research topics where Philipp Panitz is active.

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Featured researches published by Philipp Panitz.


symposium on cloud computing | 2011

A gate sizing method for glitch power reduction

Lei Wang; Markus Olbrich; Erich Barke; Thomas Büchner; Markus Bühler; Philipp Panitz

Due to the difficulty in estimating dynamic power at the gate level, a quantity called power metric and its efficient calculation method are introduced in this work. Based on the proposed power metric, a heuristic gate sizing algorithm for glitch power reduction is proposed for semi-custom design. The proposed heuristic algorithm minimizes the total power metric of a circuit. According to the experimental results on 8 ISCAS85 benchmark circuits and 5 real industrial circuits, more than 30% average glitch power reduction and 15.5% average total power reduction can be achieved by means of the proposed algorithm, respectively. The achieved improvements on power and area both are more than those by means of conventional gate sizing algorithms.


international conference on computer aided design | 2011

A theoretical probabilistic simulation framework for dynamic power estimation

Lei Wang; Markus Olbrich; Erich Barke; Thomas Büchner; Markus Bühler; Philipp Panitz

As fast non-simulation-based power estimation techniques, probabilistic simulation techniques were widely researched in the 1990s. Spatial and temporal correlations are commonly known as two fundamental challenges of these kinds of techniques. Previous work showed that spatial correlation could be coped with by means of bit-parallel simulation. For temporal correlation that has great impact on estimating glitches, previous work only showed that it could be considered by means of a glitch-filtering scheme which is an approximation algorithm, but did not answer the question whether temporal correlation could be overcome without any approximation. Our work extends conventional probabilistic simulation techniques and puts the essentials and extensions of probabilistic simulation into a theoretical framework. Based on the framework, this paper shows that modeling temporal correlation in probabilistic simulation without any approximation is only possible in theory. Therefore, an improved approximation of the exact method is proposed. Compared to the conventional probabilistic simulation, our prominently improved results prove the effectiveness of our approximation algorithm. At the end of this paper, the advantages and the bottlenecks of probabilistic simulation are concluded in general.


Archive | 2011

Method and data processing unit for calculating at least one multiply-sum of two carry-less multiplications of two input operands, data processing program and computer program product

Maarten J. Boersma; Jens Leenstra; Tim Niggemeier; Philipp Oehler; Philipp Panitz


Archive | 2012

Gate configuration determination and selection from standard cell library

Thomas Buechner; Markus Buehler; Markus Olbrich; Philipp Panitz; Lei Wang


Archive | 2011

MECHANISM TO SPEED-UP MULTITHREADED EXECUTION BY REGISTER FILE WRITE PORT REALLOCATION

Maarten J. Boersma; Jens Leenstra; Tim Niggemeier; Philipp Oehler; Philipp Panitz


Archive | 2014

BYTE SELECTION AND STEERING LOGIC FOR COMBINED BYTE SHIFT AND BYTE PERMUTE VECTOR UNIT

Jens Leenstra; Philipp Panitz; Christoph Wandel


Archive | 2012

GLITCH POWER REDUCTION

Thomas Buechner; Markus Buehler; Markus Olbrich; Philipp Panitz; Lei Wang


Archive | 2009

Method and system for calculating timing delay in a repeater network in an electronic circuit

Markus Buehler; Juergen Kuehl; Markus Olbrich; Philipp Panitz


Archive | 2012

Estimating power consumption of an electronic circuit

Thomas Buechner; Markus Buehler; Philipp Panitz; Lei Wang; Markus Olbrich


Archive | 2008

Routing of wires of an electronic circuit

Markus Buehler; Juergen Koehl; Markus Olbrich; Philipp Panitz

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