Philippe Faes

Scalable hardware accelerator for comparing DNA and protein sequences

Comparing genetic sequences is a well-known problem in bioinformatics. Newly determined sequences are being compared to known sequences stored in databases in order to investigate biological functions. In recent years the number of available sequences has increased exponentially. Because of this explosion a speedup in the comparison process is highly required. To meet this demand we implemented a dynamic programming algorithm for sequence alignment on reconfigurable hardware. The algorithm we implemented, Smith-Waterman-Gotoh (SWG) has not been implemented in hardware before. We show a speedup factor of 40 in a design that scales well with the size of the available hardware. We also demonstrate the limits of larger hardware for small problems, and project our design on the largest Field Programmable Gate Array (FPGA) available today.

FPGA-aware garbage collection in Java

During codesign of a system, one still runs into the impedance mismatch between the software and hardware worlds. This paper identifies the different levels of abstraction of hardware and software as a major culprit of this mismatch. For example, when programming in high-level object-oriented languages like Java, one has disposal of objects, methods, memory management, that facilitates development but these have to be largely abandoned when moving the same functionality into hardware. As a solution, this paper presents a virtual machine, based on the Jikes Research Virtual Machine, that is able to bridge the gap by providing the same capabilities to hardware components as to software components. This seamless integration is achieved by introducing an architecture and protocol that allow reconfigurable hardware and software to communicate with each other in a transparent manner i.e. no component of the design needs to be aware whether other components are implemented in hardware or in software. Further, in this paper we present a novel technique that allows reconfigurable hardware to manage dynamically allocated memory. This is achieved by allowing the hardware to hold references to objects and by modifying the garbage collector of the virtual machine to be aware of these references in hardware. We present benchmark results that show, for four different, well-known garbage collectors and for a wide range of applications, that a hardware-aware garbage collector results in a marginal overhead and is therefore a worthwhile addition to the developers toolbox.

Mobility of Data in Distributed Hybrid Computing Systems

In distributed hybrid computing systems, traditional sequential processors are loosely coupled with reconfigurable hardware for optimal performance. This loose coupling proves to be a communication challenge; the processor units cannot efficiently share a physical memory. This paper proposes a distributed shared memory architecture and a method for effective data migration within that shared memory. Data is moved using a novel garbage collection scheme, the dual semispace collector. The new garbage collector and the distributed memory prove to be an effective means of data migration in distributed hybrid computing systems.

Using method interception for hardware/software co-development

In many embedded systems, the computational power of an instruction set processor is combined with hardware accelerators. Building such combined systems implies co-design of the software that runs on the processor and the hardware that accelerates the embedded application. During the co-design process, the application is partitioned into a software part (running on the processor) and a hardware part (running on the accelerator). In order to ease the iterative process of partitioning, we introduce a novel design methodology. In our methodology, the interface between hardware and software is transparent to the software designer, and is based on dynamic method interception. Because the interface is transparent and generated automatically, the initial all-software prototype of the system can more easily be refined and partitioned. We show that method interception is inexpensive, and we demonstrate method interception in a real-life application.Using our methodology, embedded systems can be designed fast, reducing time-to-market, while still achieving a high run-time performance.