Philippe Matagne

Superior Reliability of Junctionless pFinFETs by Reduced Oxide Electric Field

Superior reliability of junctionless (JL) compared with inversion-mode field-effect transistors (FETs) is experimentally demonstrated on bulk FinFET wafers. The reduced negative bias temperature instability (NBTI) of JL pFETs outperforms the previously reported best NBTI reliability data obtained with Si channel devices and guarantees 10-year lifetime at typical operating voltages and high temperature. This behavior is understood through the reduced oxide electric field and lessened interaction between charge carriers and oxide traps during device operation. These findings encourage the investigation of JL devices with alternative channels as a promising alternative for 7-nm technology nodes meeting reliability targets.

Modeling of Via Resistance for Advanced Technology Nodes

We investigate the dependence of Cu via resistance on via dimensions, shape, misalignment, and Co via prefill level by means of a novel resistivity model, calibrated to actual wires on silicon and integrated into the Synopsys Raphael tool. For this paper, we consider the case of 16 and 12nm self-aligned vias, which are representative for the 7 and 5nm logic technology nodes, respectively. Process emulations are performed by using the Synopsys Sentaurus Process Explorer tool in order to generate 3-D models of the investigated via structures. Finally, via resistance is extracted through current simulations in Raphael, that is, by taking into account the actual conductive path from the wires into the via. We predict that via resistance could increase by more than a factor of 2 from node to node. We show that chamfered vias can exhibit up to 56% less resistance than standard (87° tapered) vias because of the larger cross section at the via top. For the same reason, via resistance sensitivity to via width variations along the direction of the connecting (i.e. upper) wire is smaller for chamfered vias. As far as via misalignment to the connected (i.e. lower) wire is concerned, we demonstrate that in the range of interest, the induced resistance increase is not severe (e.g. 20% or lower), and in particular, via resistance is not inversely proportional to the contact area between the via and the connected wire. If side contact to the connected wire is enabled upon misalignment, the via resistance increase is further reduced. If vias are fully self-aligned, that is, self-aligned to both connecting and connected wires, the impact of misalignment can be neutralized in a certain range by properly oversizing the via mask in the direction along the connecting wire. Finally, we show that Co via prefill can enable a substantial reduction (up to 45%) of via resistance for chamfered vias, where the bottom barrier surface can be significantly increased when raised to the via top by means of the prefill step.

Zero-thickness multi work function solutions for N7 bulk FinFETs

A novel multi work function process is used to demonstrate up to 250 mV effective work function shifts of nMOS devices. The process use SiH4-soak of ALD TiN to change its barrier properties with ALD TiAl. FinFET devices are demonstrated with ~100 mV VT-shift for 24-nm-LG devices resulting in 20× reduction in off-state leakage at unaffected sub threshold slope and improved mismatch behavior. A patterning scheme using an nMOS first RMG process is proposed and demonstrated.

Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells

We report a comprehensive evaluation of junctionless (JL) vs. conventional inversion-mode (IM) gate-all-around (GAA) nanowire FETs (NWFETs) with the same lateral (L) configuration. Lower I_OFF values and excellent electrostatics can be obtained with optimized NW doping for a given JL NW size (W_NW≤25nm, H_NW~22nm), with increased doping enabling ION improvement without I_OFF penalty for W_NW ≤10nm. These devices also appear as a viable option for analog/RF, showing similar speed and voltage gain, and reduced LF noise as compared to IM NWFETs. V_T mismatch performance shows higher A_VT with increased NW doping for JL NMOS, with less impact seen for PMOS and at smaller NWs. The JL concept is also demonstrated in vertical (V) GAA-NWFETs with in-situ doped Si epi NW pillars (d_NW≥20-30nm), integrated on the same 300mm Si platform as lateral devices. Low I_OFF, I_G, and good electrostatics are achieved over a wide range of VNW arrays. Lastly, a novel SRAM design is proposed, taking advantage of the JL process simplicity, by vertically stacking two VNWFETs (n/n or p/p) to reduce SRAM area per bit by 39%.

Challenges and opportunities of vertical FET devices using 3D circuit design layouts

We report on vertical nanowire FET devices (VNWFETs) with a gate-all-around (GAA) configuration, which offer promising opportunities to enable further CMOS scaling and increased circuit layout efficiency. They allow up to 30% denser SRAM bitcells with improved read and write stability, smaller minimum operating voltages (Vmin), and lower standby leakage values as compared to cells built with lateral GAA-NWFETs. Furthermore, vertical stacking of these devices also opens the path for SRAM 3D scaling, with a design presented here that can enable, with two levels of transistors in the vertical direction, to reduce by 39% the SRAM area per bit. The two vertically stacked VNWFETs are of the same doping type (n/n or p/p), and a lower complexity of implementation may be possible by taking advantage of the junctionless (JL) concept and its process simplicity, a topic also explored in this work.

Rigorous assessment of patterning solution of metal layer in 7 nm technology node

Abstract. In a 7 nm node (N7), the logic design requires a critical poly pitch of 42 to 45 nm and a metal 1 (M1) pitch of 28 to 32 nm. Such high-pattern density pushes the 193 immersion lithography solution toward its limit and also brings extremely complex patterning scenarios. The N7 M1 layer may require a self-aligned quadruple patterning (SAQP) with a triple litho-etch (LE3) block process. Therefore, the whole patterning process flow requires multiple exposure+etch+deposition processes and each step introduces a particular impact on the pattern profiles and the topography. In this study, we have successfully integrated a simulation tool that enables emulation of the whole patterning flow with realistic process-dependent three-dimensional (3-D) profile and topology. We use this tool to study the patterning process variations of the N7 M1 layer including the overlay control, the critical dimension uniformity budget, and the lithographic process window (PW). The resulting 3-D pattern structure can be used to optimize the process flow, verify design rules, extract parasitics, and most importantly, simulate the electric field, and identify hot spots for dielectric reliability. As an example application, the maximum electric field at M1 tip-to-tip, which is one of the most critical patterning locations, has been simulated and extracted. The approach helps to investigate the impact of process variations on dielectric reliability. We have also assessed the alternative M1 patterning flow with a single exposure block using extreme ultraviolet lithography (EUVL) and analyzed its advantages compared to the LE3 block approach.

Transistors on two-dimensional semiconductors: contact resistance limited by the contact edges

We report for the first time a TCAD investigation on the spatial distribution of carrier injection at MoS2 contacts. The proposed semi-classical approach successfully captures the experimentally observed contact behavior. Using the model, we identify that for monolayer and bilayer MoS2, the carriers are injected at the edge of the contact metal, resulting in a high contact resistance. The primary cause of this high resistance is carrier depletion under the contacts, which is not alleviated at degenerate doping under the contacts.

Accurate prediction of device performance in sub-10nm WFIN FinFETs using scalpel SSRM-based calibration of process simulations

In this paper, we illustrate how high resolution two-dimensional (2D) carrier maps obtained from scalpel scanning spreading resistance microscopy (s-SSRM) can be applied to calibrate a technology computer aided design (TCAD) simulator in order to predict and understand the performance of sub-10nm WFIN FinFETs. In the proposed approach, process simulations are calibrated such that the resulting simulated carrier profiles match the quantified s-SSRM profiles. Upon reaching satisfactory agreement, they can be used as input for device simulators in order to predict more accurately key device parameters such as the linear on-state resistance (RON, LIN), and the threshold voltage (VT, SAT) roll-off to name few. This also allows us to accelerate the development of devices towards new technology nodes (as N7 and N5) by identifying parameters to be improved and technological options to be selected.