A. Veloso

Review of FINFET technology

Although at single transistor and small circuits level, FINFET technology has been demonstrated to be an attractive option for advanced technology nodes, there are still important challenges to face like reduction of access resistance and the implementation of strain boosters in both NMOS and PMOS FINFET devices. The high performance sensitivity to fin dimensions (width, height, LER) sets up very tight restrictions for the process control which may create a big challenge to demonstrate process manufacturability.

Vertical GAAFETs for the Ultimate CMOS Scaling

In this paper, we compare the performances of FinFETs, lateral gate-all-around (GAA) FETs, and vertical GAAFETs (VFETs) at 7-nm node dimensions and beyond. Comparison is done at ring oscillator level accounting not only for front-end of line devices but also for interconnects. It is demonstrated that FinFETs fail to maintain the performance at scaled dimensions, while VFETs demonstrate good scalability and eventually outperform lateral devices both in speed and power consumption. Lateral GAAFETs show better scalability with respect to FinFETs but still consume 35% more energy per switch than VFETs if made under 5-nm node design rules.

A functional 41-stage ring oscillator using scaled FinFET devices with 25-nm gate lengths and 10-nm fin widths applicable for the 45-nm CMOS node

In this letter, we have fabricated a functional FinFET ring oscillator with a physical gate length of 25 nm and a fin width of 10 nm, the smallest ever reported. We demonstrate that these narrow (W/sub fin/ = 10 nm) and tall (H/sub fin/ = 60 - 80 nm) fins can be reliably etched with controlled profiles and that they are required to keep the short-channel effects under control, resulting in drain-induced barrier leakage characteristics of 45 mV/V at V/sub dd/ = 1 V and L/sub g/ = 25 nm for the nFET. For these ultrathin (10 nm) fins, we have succeeded in properly setting the V/sub T/ at 0.2 V without the use of metal gates. In addition to ring oscillators, we also have obtained excellent pFET FinFET devices at wider fin widths (W/sub fin/ = 65 nm) with I/sub dsat/ = 380 /spl mu/A//spl mu/m at I/sub off/ = 60 nA//spl mu/m and V/sub dd/ = -1.2 V.

Demonstration of fully Ni-silicided metal gates on HfO/sub 2/ based high-k gate dielectrics as a candidate for low power applications

We have fabricated fully Ni-silicided metal gate (FUSI) CMOS devices with HfO2-based gate dielectrics for the first time. We demonstrate that full silicidation eliminates the Fermi level pinning at the polySi-HfO2 dielectric interface in pFETs. For nMOS devices, a 5 orders of magnitude reduction in short channel sub-threshold leakage is obtained with similar drive current compared to the poly gate devices. In addition, the FUSI process does not degrade the hysterisis nor the dielectric breakdown. This result makes FUSI on high-K a strong candidate for scaled low power technologies.

The Dependence of Retention Time on Gate Length in UTBOX FBRAM With Different Source/Drain Junction Engineering

The floating-body-RAM sense margin and retention-time dependence on the gate length is investigated in UTBOX devices using BJT programming combined with a positive back bias (so-called V th feedback). It is shown that the sense margin and the retention time can be kept constant versus the gate length by using a positive back bias. Nevertheless, below a critical L, there is no room for optimization, and the memory performances suddenly drop. The mechanism behind this degradation is attributed to GIDL current amplification by the lateral bipolar transistor with a narrow base. The gate length can be further scaled using underlap junctions.

Scalability of Ni FUSI gate processes: phase and Vt control to 30 nm gate lengths

We demonstrate for the first time the scalability of NiSi and Ni/sub 3/Si FUSI gate processes down to 30 nm gate lengths, with linewidth independent phase and V/sub t/ control. We show that 1-step FUSI is inadequate for NiSi FUSI gates, because it results in incomplete silicidation at low thermal budgets or in a linewidth dependent Ni silicide phase - inducing V/sub t/ shifts - at higher thermal budgets. We show that V/sub t/ and WF shifts are larger on high-K (HfO/sub 2/ (250 mV) or HfSiON (330mV)) than on SiON (110mV) and report Fermi level unpinning for Ni-rich FUSI on high-K. In contrast, we demonstrate the scalability of Ni/sub 3/Si FUSI, with no phase control issues, and report HfSiON Ni/sub 3/Si FUSI PMOS devices with V/sub t/= -0.33 V. Lastly, we show that, for NiSi, phase control down to narrow gate lengths can be obtained with a 2-step FUSI process.

Junction Field Effect on the Retention Time for One-Transistor Floating-Body RAM

One-transistor floating-body random access memory retention time distribution is investigated on silicon-on-insulator UTBOX devices. It is shown that the average retention time can be improved by two to three orders of magnitude by reducing the body-junction electric field. However, the retention time distribution, which is mainly caused by the generation-recombination center density variation, remains similar.

CMOS integration of dual work function phase controlled Ni FUSI with simultaneous silicidation of NMOS (NiSi) and PMOS (Ni-rich silicide) gates on HfSiON

We demonstrate for the first time CMOS integration of dual WF (work function) metal gates on HfSiON using Ni-phase controlled FUSI. The novel integration scheme that we demonstrate uses our optimized 2-step Ni FUSI process (1) for simultaneous full silicidation of nMOS and pMOS, achieving different Ni/Si ratios on nMOS and pMOS by reduction of the pMOS poly height through a selective and controlled poly etch back prior to gate silicidation. This novel integration scheme offers the advantages of 1) simplicity (same Ni deposition and silicidation process on nMOS and pMOS), 2) large process window for poly etch-back process (same pMOS characteristics for poly thickness variation of 50%), 3) WF and Vt tuning on HfSiON by phase control, with 4) scalable, linewidth independent suitable Vts for nMOS (0.5 V) and pMOS (-0.3 V), and 5) solves process yield issues of Ni-rich silicides related to volume expansion, stress, filaments and voiding, resulting in a continuous silicide that is nicely confined between the sidewall spacers. Ring oscillator operation was also demonstrated

Stress simulations for optimal mobility group IV p- and nMOS FinFETs for the 14 nm node and beyond

Calculations of stress enhanced mobilities are performed for n- and p-FinFETs with both Si and Ge channels for the 14 nm node and beyond. Relaxed Ge p-FinFETs and even Ge with a GeSn5% source / drain stressor cannot outperform strained Si. However, growing the Ge channel strained on a SiGe75% strain relaxed buffer (SRB) provides a 49% mobility boost over strained Si. For Si n-FinFETs, SRB mobility boost is also possible, with Si on a SiGe 25% SRB improving mobility by 83%. Addition of a Si:C 2% S/D stressor increases that benefit to 109%. For Ge n-FinFETs, relaxed channels outperform strained Si by 120%, owing primarily to the 6× increase in fin sidewall mobility. Adding a SiGe 75% S/D stressor increases that benefit to 210%. In general, the SRB stressors have excellent scalability to future nodes. TCAD trends are qualitatively confirmed by Nano-Beam Diffraction.

Flexible and robust capping-metal gate integration technology enabling multiple-VT CMOS in MuGFETs

We report, for the first time, a comprehensive study on various capping integration options for WF engineering in MuGFET devices with TiN gate electrode: HfSiO/cap/TiN, cap/HfSiO/TiN and HfSiO/TiN/cap/TiN vs. reference deposition sequence HfSiO/TiN (cap = Al2O3 for pmos, and Dy2O3 or La2O3 for nmos). We show that: 1) low-VT values (Lt 0.3 V) are achieved for both nmos and pmos, with excellent process control and device behavior down to Lg ap 50 nm and WFIN ap 20 nm, for optimized gate stack configurations; 2) inserting a cap layer in-between TiN layers instead of HfSiO/cap/TiN leads to improved mobility, reduced CET without impacting JG, similar noise response and improved BTI behavior, with correction of the abnormal PBTI degradation seen for HfSiO/DyO/TiN. Is also enables simplified and more robust CMOS co-integration of low- and med-VT devices in the same wafer, avoiding loss in CET and damage of the host dielectric with the cap removal process.