Philippe Thissen

Image compression by self-organized Kohonen map

This paper presents a compression scheme for digital still images, by using the Kohonens neural network algorithm, not only for its vector quantization feature, but also for its topological property. This property allows an increase of about 80% for the compression rate. Compared to the JPEG standard, this compression scheme shows better performances (in terms of PSNR) for compression rates higher than 30.

A CMOS analog circuit for Gaussian functions

A simple CMOS analog circuit that performs the Gaussian function for classification applications is introduced. Combining the exponential characteristics of MOS transistors in weak inversion and the square characteristics in strong inversion the function is built. Design constraints and mismatch effects are discussed, as well as the layout optimization. The circuit has been designed in a SOI technology and manufactured. Good experimental results are obtained which shows that the circuit is suitable to be included as a building block of an IC to perform classification tasks or other possible applications.

An analog processor architecture for a neural network classifier

Many neural-like algorithms currently under study support classification tasks. Several of these algorithms base their functionality on LVQ-like procedures to find locations of centroids in the data space, and on kernel (or radial-basis) functions centered on these centroids to approximate functions or probability densities. A generic analog chip could implement in a parallel way all basic functions found in these algorithms, permitting construction of a fast, portable classification system.<<ETX>>

Linear Vector Classification: An Improvement on LVQ Algorithms to Create Classes of Patterns

Learning Vector Quantization algorithms (LVQ1 and LVQ2), proposed by Kohonen, are widely used for the quantization and the classification of vectors into clusters. These algorithms quantize each class of vectors in the space into a defined number of ‘prototypes’. Despite an efficient quantization of the stimuli space, these algorithms are not well adapted to classification tasks where the distribution of prototypes inside a single class is not important, provided that the boundaries between classes are adequately approximated through the prototypes. We propose here an adaptation of the LVQ1 algorithm where the resulting prototypes will approximate the boundaries between classes; by this way, stimuli located as well near the border as in the center of a class will be correctly classified, even if they are not adequately quantified in the sense of ‘Vector Quantization’.

Analog VLSI implementation of kernel-based classifiers

Kernel-based classifiers are neural networks (radial basis functions) where the probability densities of each class of data are first estimated, to be used thereafter to approximate Bayes boundaries between classes. Such an algorithm however involves a large number of operations, and its parallelism makes it an ideal candidate for a dedicated VLSI implementation. The authors present in this paper the architecture for a dedicated processor for kernel-based classifiers, and the implementation of the original cells.

Matching properties of CMOS SOI transistors

Analog implementations of neural networks have shown promising results; the main drawback of such techniques is the limited accuracy available in standard analog technologies. A test circuit composed of 256 N-channel and P-channel transistors has been designed and tested in an SOI (Silicon-On-Insulator) CMOS 3 /spl mu/m technology. This paper describes the matching properties of these current sources. We present results about mismatching depending on proximity and operating conditions. We also propose a method to compute the matching behavior of multiple current mirrors.

A Practical View of Suboptimal Bayesian Classification with Radial Gaussian Kernels

For pattern classification in a multi-dimensional space, the minimum misclassification rate is obtained by using the Bayes criterion. Kernel estimators or probabilistic neural networks provide a good way to evaluate the probability densities of each class of data and are an interesting parallel implementation of the Bayesian classifier [1]. However, their training procedure leads to a very high number of neurons when large datasets are available; the classifier then becomes too complex and time consuming for on-line operation. Suboptimal Bayesian classifiers based on radial Gaussian kernels [2] uses an iterative unsupervised learning method based on vector quantization to obtain a significant simplification of the network structure, while keeping sufficiently accurate estimations of probability densities. In this paper, we study the vector quantization problem and the effects of codebook size and data space dimension on the optimal width factors of the radial Gaussian kernels used in the estimation.

A VLSI System for Neural Bayesian and LVQ Classification

Various types of neural networks ma! be used in multi-dimensional classification tasks; among them, Bayesian and LVQ algorithms are interesting respectively for their performances and their simplicity of operations, The large number of operations involved in such algorithms may however be incompatible with on-line applications or with the necessity of portable small size systems. This paper describes a neural network classifier system based on a fully analog operative chip coupled with a digital control system, The chip implements sub-optimal Bayesian classifier and LVQ algorithms.

An Associative Processor Dedicated to Classification by Neural Methods

Multi-dimensional classification tasks by neural methods are interesting for their performances and their simplicity of operations. However. the number of computations needed by these algorithms is very impressive and drastically limits practical applications of such methods. This paper describes a digital bit-serial, massively parallel associative processor to speed up neural-like classification tasks. To achieve this goal, each block of this associative processor is optimized to the main operations involved in classification algorithms.