Jordi Madrenas

The Perplexus bio-inspired reconfigurable circuit

This paper introduces the ubichip, a custom reconfigurable electronic device capable of implementing bio- inspired circuits featuring growth, learning, and evolution. The ubichip is developed in the framework of Perplexus, a European project that aims to develop a scalable hardware platform made of bio-inspired custom reconfigurable devices for simulating large-scale complex systems. In this paper, we describe the configurability and architectural mechanisms that will allow the implementation of evolv- able and developmental cellular and neural systems in an efficient way. These mechanisms are dynamic routing, self- reconfiguration, and a neural-friendly logic cells architecture.

Synchronization of nonlinear electronic oscillators for neural computation

This paper deals with coupled oscillators as the building blocks of a bioinspired computing paradigm and their implementation. In order to accomplish the low-power and fast-processing requirements of autonomous applications, we study the microelectronic analog implementation of physical oscillators, instead of the software computer-simulated implementation. With this aim, the original oscillator has been adapted to a suitable microelectronic form. So as to study the hardware nonlinear oscillators, we propose two macro models, demonstrating that they preserve the synchronization properties. Secondary effects such as mismatch and output delay and their relation to network synchronization are analyzed and discussed. We show the correct operation of the proposed electronic oscillators with simulations and experimental results from a manufactured integrated test circuit. The proposed architecture is intended to perform the scene segmentation stage of an autonomous focal-plane self-contained visual processing system for artificial vision applications.

A CMOS analog circuit for Gaussian functions

A simple CMOS analog circuit that performs the Gaussian function for classification applications is introduced. Combining the exponential characteristics of MOS transistors in weak inversion and the square characteristics in strong inversion the function is built. Design constraints and mismatch effects are discussed, as well as the layout optimization. The circuit has been designed in a SOI technology and manufactured. Good experimental results are obtained which shows that the circuit is suitable to be included as a building block of an IC to perform classification tasks or other possible applications.

Scene segmentation using neuromorphic oscillatory networks

Using the neuromorphic approach, we propose an analog very large-scale integration (VLSI) implementation of an oscillatory segmentation algorithm based on local excitatory couplings and global inhibition. The original model has been simplified and adapted for its efficient VLSI implementation while preserving its segmentation properties. To demonstrate the feasibility of the approach, a 16/spl times/16-pixel testchip has been manufactured. Extensive experimental results demonstrate that it can properly segment binary images. Power consumption, segmentation time per cell, and system complexity are very low compared to other hardware and software implementation schemes. We also show two main differences between the original algorithm and the analog approach. First, the network is noise tolerant without the need of additional elements and second, delays between oscillators due to the combination of mismatch and output capacitances have to be accounted for network performance.

An analog processor architecture for a neural network classifier

Many neural-like algorithms currently under study support classification tasks. Several of these algorithms base their functionality on LVQ-like procedures to find locations of centroids in the data space, and on kernel (or radial-basis) functions centered on these centroids to approximate functions or probability densities. A generic analog chip could implement in a parallel way all basic functions found in these algorithms, permitting construction of a fast, portable classification system.<<ETX>>

Energy optimization of tapered buffers for CMOS on-chip switching power converters

This work presents a model to determine the power consumption of tapered buffers, validating its results with transistor-level simulations. Focusing on their application as gate drivers for high-frequency on-chip switching power converters, the need for a fall-rise time evaluation at the output of the tapered buffer is discussed. Consequently, the output fall-rise time is modeled and validated by means of simulations. Given the linear relation between the fall-rise time and the switching losses of the power MOSFET, an optimized design procedure is proposed to concurrently minimize the switching losses of the tapered buffer together with the power MOSFET switching losses. The work concludes with a design example for a 15000 /spl mu/m-width PMOS transistor, presenting an optimum tapering factor of 21, for a specific 0.35 /spl mu/m standard CMOS technology.

A Translinear, Log-Domain FPAA on Standard CMOS Technology

A field-programmable analog array (FPAA) using a standard-CMOS wide-dynamic-range translinear element (TE) is introduced. The FPAA configurable analog blocks (CABs) are based on a reconfigurable translinear cell (RTC), capable of implementing the basic circuit elements required by translinear and log-domain circuit design. The interfacing is provided by an I/O programmable cell, which allows for easier connectivity between the signal-processing core and the external circuitry. As a proof-of-concept, a 5 × 5 RTC FPAA testchip was implemented in 0.35- μm CMOS technology. A set of various circuit primitives, such as one- and four-quadrant multipliers, an Euclidean distance operator and a fourth-order log-domain filter, were mapped on the chip in order to demonstrate the versatility of the approach. FPAA bandwidth reaches 20 MHz with a power consumption of 30 μW/TE and precision errors below 3%.

Integration of GMR Sensors with Different Technologies

Less than thirty years after the giant magnetoresistance (GMR) effect was described, GMR sensors are the preferred choice in many applications demanding the measurement of low magnetic fields in small volumes. This rapid deployment from theoretical basis to market and state-of-the-art applications can be explained by the combination of excellent inherent properties with the feasibility of fabrication, allowing the real integration with many other standard technologies. In this paper, we present a review focusing on how this capability of integration has allowed the improvement of the inherent capabilities and, therefore, the range of application of GMR sensors. After briefly describing the phenomenological basis, we deal on the benefits of low temperature deposition techniques regarding the integration of GMR sensors with flexible (plastic) substrates and pre-processed CMOS chips. In this way, the limit of detection can be improved by means of bettering the sensitivity or reducing the noise. We also report on novel fields of application of GMR sensors by the recapitulation of a number of cases of success of their integration with different heterogeneous complementary elements. We finally describe three fully functional systems, two of them in the bio-technology world, as the proof of how the integrability has been instrumental in the meteoric development of GMR sensors and their applications.

Experiments on the Release of CMOS-Micromachined Metal Layers

We present experimental results on the release of MEMS devices manufactured using the standard CMOS interconnection metal layers as structural elements and the insulating silicon dioxide as sacrificial layers. Experiments compare the release results of four different etching agents in a CMOS technology (hydrofluoric acid, ammonium fluoride, a mixture of acetic acid and ammonium fluoride, and hydrogen fluoride), describe various phenomena found during the etching process, and show the release results of multilayer structures.

Minimum time control of a buck converter by means of fuzzy logic approximation

This paper investigates the use of fuzzy logic to implement some nonlinear control laws in bidirectional power converters. The authors design a minimum time control scheme of a buck power converter by means of fuzzy logic approximation. The proposed controller is implemented by means of an analog hardware architecture which is able to efficiently implement neuro-fuzzy models. By combining the main features of digital and analog alternatives, it is possible to provide a high degree of flexibility (in terms of number of inputs, number of membership functions per input and number of fuzzy rules) when handling real world tasks. Also, the authors have created a program for validating, via software, the proposed architecture. Computer simulation results for a buck power converter structure illustrate the design and the implementation. VLSI ASIC mixed-mode implementation details are also included.