Phillip J. Kuekes

Teramac-configurable custom computing

Prototypes are invaluable for studying special purpose parallel architectures and custom computing. We have built a configurable custom computing engine, based on field programmable gate arrays, to enable experiments on an interesting scale. The Teramac configurable hardware system can execute synchronous logic designs of up to one million gates at rates up to one megahertz. Search and retrieval of nontext data from very large databases can be greatly accelerated using special purpose parallel hardware. We are using Teramac to conduct experiments with special purpose processors involving search of nontext databases.

Plasma: An FPGA for Million Gate Systems

Prototypes are invaluable for studying special purpose parallel architectures and custom computing. This paper describes a new FPGA, called Plasma- the heart of a configurable custom computing engine (Teramac) that can execute synchronous logic designs up to one million gates at rates up to one megahertz. Plasma FPGAs using 0.8 micron CMOS are packaged in large multichip modules (MCMs). A large custom circuit may be mapped onto the hardware in approximately two hours, without user intervention. Plasma introduces some innovative architecture concepts including hardware support for large multiported register files.

On the integration of memristors with CMOS using nanoimprint lithography

Memristors were vertically integrated with CMOS circuits using nanoimprint lithography (NIL), making a transistor/memeristor hybrid circuit. Several planarization technologies were developed for the CMOS substrates to meet the surface planarity requirement for NIL. Accordingly, different integration schemes were developed and optimized. UV-curable NIL (UV-NIL) using a double layer spin-on resists was carried out to pattern the electrodes for memristors. This is the first demonstration of NIL on active CMOS substrates that are fabricated in a CMOS fab. Our work demonstrates that NIL is compatible with commercial IC fabrication process. It was also demonstrated that the memristors are integratable with traditional CMOS to make hybrid circuits without changing the current infrastructure in IC industry.

Effect of Conductance Variability on Resistor-Logic Demultiplexers for Nanoelectronics

On a mixed-scale nanoelectronic crossbar, in which nanowires cross CMOS-scale wires at right angles, a demultiplexer circuit may be laid out using configurable resistors at the crosspoint junctions. This circuit can function as an interface between conventional CMOS microelectronic circuitry and the smaller nanocircuitry by allowing a few CMOS address lines to control a much larger number of nanowires. The voltage margin properties of these resistor-demultiplexers can be improved by basing them on error-correcting codes. In any real fabrication process, the conductances of the resistors in the demultiplexer circuit will be distributed over a range of values. Using simulation, we investigate how variability in the conductances affects the voltages on the output lines of the demultiplexer, and the related voltage margin of the overall circuit. The simulation results provide a simple quantitative relationship revealing that the voltage variability is smaller than the component variability

Defect Tolerance Based on Coding and Series Replication in Transistor-Logic Demultiplexer Circuits

We present a family of defect tolerant transistor-logic demultiplexer circuits that can defend against both stuck-ON (short defect) and stuck-OFF (open defect) transistors. Short defects are handled by having two or more transistors in series in the circuit, controlled by the same signal. Open defects are handled by having two or more parallel branches in the circuit, controlled by the same signals, or more efficiently, by using a transistor-replication method based on coding theory. These circuits are evaluated, in comparison with an unprotected demultiplexer circuit, by: 1) modeling each circuits ability to tolerate defects and 2) calculating the cost of the defect tolerance as each circuits redundancy factor R, which is the relative number of transistors required by the circuit. The defect-tolerance model takes the form of a function giving the failure probability of the entire demultiplexer circuit as a function of the defect probabilities of its component transistors, for both defect types. With the advent of defect tolerance as a new design goal for the circuit designer, this new form of performance analysis has become necessary.

An FPGA for multi-chip reconfigurable logic

The Plasma chip, designed specifically to address issues important to custom computing machines (CCM), completes a 100% fully automatic place and route in approximately three seconds. Plasma FPGAs using 0.8 micron CMOS are packaged in large multichip modules (MCMs). Plasma introduces some innovative architecture concepts including hardware support for large multiported register files.

Expanding Human Cognition and Communication

In order to chart the most profitable future directions for societal transformation and corresponding scientific research, five multidisciplinary themes focused on major goals have been identified to fulfill the overall motivating vision of convergence described in the previous pages. The first, “Expanding Human Cognition and Communication,” is devoted to technological breakthroughs that have the potential to enhance individuals’ mental and interaction abilities. Throughout the twentieth century, a number of purely psychological techniques were offered for strengthening human character and personality, but evaluation research has generally failed to confirm the alleged benefits of these methods (Druckman and Bjork 1992; 1994). Today, there is good reason to believe that a combination of methods, drawing upon varied branches of converging science and technology, would be more effective than attempts that rely upon mental training alone.