Pi-Chun Juan
National Tsing Hua University
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Publication
Featured researches published by Pi-Chun Juan.
Journal of Applied Physics | 2008
Wen-Chieh Shih; Pi-Chun Juan; Joseph Ya-min Lee
Metal-ferroelectric-insulator-semiconductor (MFIS) field effect transistors with Pb(Zr0.53,Ti0.47)O3 (PZT) ferroelectric layer and yttrium oxide Y2O3 insulator layer were fabricated. The maximum C-V memory window of 1.5V was obtained at a sweep voltage of 8V. The dominating conduction mechanism through the MFIS structure is Schottky emission in the temperature range from 300to450K. The nonvolatile operation of MFIS transistors was demonstrated by applying positive/negative writing pulses. The retention shows that the transistors maintain a threshold voltage window of 1.2V without deterioration after 3×103s. The low leakage current and the high effective Y2O3∕Si barrier height of 1.85eV can well explain the size of memory window and retention properties. The effect of charge injection is reduced in this structure.
Applied Physics Letters | 2009
Chih-Ming Lin; Wen-Chieh Shih; Ingram Yin-Ku Chang; Pi-Chun Juan; Joseph Ya-min Lee
Metal-ferroelectric-insulator-semiconductor capacitors and field effect transistors with Al/BiFeO3/Y2O3/Si structure were fabricated and characterized for nonvolatile memory applications. The capacitance-voltage curves exhibit a maximum clockwise memory window of 0.92 V. The minimum leakage current density is 2×10−7 A/cm2 at an applied voltage of 5 V. The capacitance-voltage memory window as a function of the sweep voltage range was investigated. The IDS-VGS curves of metal-ferroelectric-insulator-semiconductor transistors show a maximum memory window of 0.84 V. The drain current on/off ratio maintained more than three orders of magnitude after an elapsed time of 104 s.
Journal of Applied Physics | 2005
Pi-Chun Juan; Yu-ping Hu; Fu-Chien Chiu; Joseph Ya-min Lee
Metal-ferroelectric-insulator-semiconductor (MFIS) capacitors with a Pb(Zr0.53,Ti0.47)O3 ferroelectric layer and a hafnium oxide insulator layer have been fabricated and characterized. The size of the capacitance-voltage memory windows was investigated. The memory window first increases to a saturated value of 0.7V with the sweep voltage and then decreases due to charge injection. The oxide trapped charges in the ferroelectric∕insulator layers are studied by a voltage stress method. The flatband voltage (VFB) is measured before and after the voltage stress. The ΔVFB is 0.59V at a negative stress voltage pulse of −5V for 30s. The ΔVFB under positive voltage stress was much less and was 0.06V at a stress voltage of +5V for 5min. The energy-band diagram of the MFIS structure at inversion and accumulation modes are plotted and the VFB shift can be explained by the trapping or detrapping of charges. The current-density versus stress time (J‐t) characteristics were also measured. The result is consistent with the charge trapping model.Metal-ferroelectric-insulator-semiconductor (MFIS) capacitors with a Pb(Zr0.53,Ti0.47)O3 ferroelectric layer and a hafnium oxide insulator layer have been fabricated and characterized. The size of the capacitance-voltage memory windows was investigated. The memory window first increases to a saturated value of 0.7V with the sweep voltage and then decreases due to charge injection. The oxide trapped charges in the ferroelectric∕insulator layers are studied by a voltage stress method. The flatband voltage (VFB) is measured before and after the voltage stress. The ΔVFB is 0.59V at a negative stress voltage pulse of −5V for 30s. The ΔVFB under positive voltage stress was much less and was 0.06V at a stress voltage of +5V for 5min. The energy-band diagram of the MFIS structure at inversion and accumulation modes are plotted and the VFB shift can be explained by the trapping or detrapping of charges. The current-density versus stress time (J‐t) characteristics were also measured. The result is consistent with t...
Japanese Journal of Applied Physics | 2009
Pi-Chun Juan; Chuan-hsi Liu; Cheng-li Lin; Shin-chun Ju; Main-gwo Chen; Ingram Yin-Ku Chang; Jong-hong Lu
In this work, high-κ cerium zirconate (CeZrO4) was successfully fabricated by RF magnetron cosputtering with a postannealing temperature of 850 °C. The amount of Zr in CeO2 can be well controlled by adjusting the DC power of the Zr target. X-ray photoelectron spectroscopy (XPS) shows that CeZrO4 becomes amorphous with increasing DC power. The intensity of the CeZrO4 phase increases with increasing oxygen content in the plasma. The crystalline phases were confirmed using X-ray diffraction (XRD). The dielectric constant and flatband voltage shift (ΔVFB) as functions of DC power and oxygen gas flow rate were investigated. The optimum balance between leakage and dielectric constant was considered. The leakage current densities were 3×10-3 and 3×10-5 A/cm2 obtained at +2 and -2 V biases, respectively. A relative dielectric constant (er) of 24.3 and an effective oxide thickness (EOT) of 1.7 nm were achieved.
IEEE Electron Device Letters | 2009
Ingram Yin-Ku Chang; Sheng-wen You; Pi-Chun Juan; Ming-Tsong Wang; Joseph Ya-min Lee
LaAlO3 is a promising candidate for gate dielectric of future VLSI devices. In this letter, n-channel metal-oxide-semiconductor field-effect transistors with LaAlO3 gate dielectric were fabricated, and the electron mobility degradation mechanisms were studied. The leakage current density is 7.6times10-5 A/cm2 at -1 V. The dielectric constant is 17.5. The surface-recombination velocity, the minority-carrier lifetime, and the effective capture cross section of surface states were extracted from gated-diode measurement. The rate of threshold voltage change with temperature (DeltaVT/DeltaT) from 11 K to 400 K is -1.51 mV/K, and the electron mobility limited by surface roughness is proportional to Eeff -0.66.
Journal of The Electrochemical Society | 2008
Ingram Yin-Ku Chang; Yu-Ren Hwang; Pi-Chun Juan; Joseph Ya-min Lee
Metal-oxide-semiconductor capacitors with Sm 2 O 3 dielectric film were fabricated and the temperature dependence of the conduction mechanisms was studied. The Sm 2 O 3 films were deposited by radio frequency magnetron sputtering. The thickness of Sm 2 O 3 was 18.8 nm. The dielectric permittivity and the equivalent oxide thickness of capacitors with Sm 2 O 3 film were 15.0 and 4.8 nm, respectively. The X-ray photoelectron spectroscopy analysis showed a silicate interfacial layer formed between Sm 2 O 3 and Si. When the aluminum electrode was biased positive, the dominant conduction mechanism was Schottky emission in the temperature range 475 K < T < 500 K and at an electrical field of 0.8 MV/cm < E < 1.4 MV/cm. In the temperature range 300-425 K, the dominant conduction mechanism was most likely space-charge-limited conduction. When the aluminum electrode was biased negative, the dominant conduction mechanism in the temperature range from 325 to 500 K and at an electrical field from 0.08 to 0.81 MV/cm was Schottky emission. At 77 K and with the electrical field above 0.9 MV/cm, the conduction mechanism was Fowler-Nordheim (F-N) tunneling. The Al/Sm 2 O 3 electron barrier height and the effective electronic mass calculated from Schottky emission and F-N tunneling were 0.82 eV and 0.13 m 0 , respectively.
Applied Physics Letters | 2008
De-Cheng Hsu; Ingram Yin-Ku Chang; Ming-Tsong Wang; Pi-Chun Juan; Ying-Lang Wang; Joseph Ya-min Lee
The positive bias temperature instability of n-channel metal-oxide-semiconductor field-effect transistors with ZrO2 gate dielectric was studied. It was observed that the degradation in threshold voltage (ΔVT) has an exponential dependence on the stress time in the temperature range from 25to75°C. The measurement of subthreshold slope (ΔS) during stress indicates that the degradation in VT is due to the interface trap charges Qit. The extracted activation energy of 0.3–0.5eV is related to a degradation dominated by the release of atomic hydrogen in the Si–ZrO2 interface.
Journal of Applied Physics | 2009
Ingram Yin-Ku Chang; Sheng-wen You; Main-gwo Chen; Pi-Chun Juan; Chun-Heng Chen; Joseph Ya-min Lee
LaAlO3 is a promising candidate of gate dielectric for future very large scale integration devices. In this work, metal-oxide-semiconductor capacitors and transistors with LaAlO3 gate dielectric were fabricated and the electron mobility degradation mechanisms were studied. The LaAlO3 films were deposited by radio frequency magnetron sputtering. The LaAlO3 films were examined by x-ray diffraction, secondary ion mass spectroscopy, and x-ray photoelectron spectroscopy. The temperature dependence of metal-oxide-semiconductor field-effect transistors characteristics was studied from 11 K to 400 K. The rate of threshold voltage change with temperature (ΔVT/ΔT) is −1.51 mV/K. The electron mobility limited by surface roughness is proportional to Eeff−0.66 in the electric field of 0.93 MV/cm<Eeff<2.64 MV/cm at 300 K and the phonon scattering is proportional to T−5.6 between 300 and 400 K. Soft optical phonon scattering was used to explain the extra source of phonon scattering in LaAlO3-gated n-channel metal-oxide-...
Journal of Applied Physics | 2010
Ming-Tsong Wang; De-Cheng Hsu; Pi-Chun Juan; Yu-Lin Wang; Joseph Ya-min Lee
Metal-oxide-semiconductor capacitors and n-channel metal-oxide-semiconductor field-effect transistors with La2O3 gate dielectric were fabricated. The positive bias temperature instability was studied. The degradation of threshold voltage (ΔVT) showed an exponential dependence on the stress time in the temperature range from 25 to 75 °C. The degradation of subthreshold slope (ΔS) and gate leakage (IG) with stress voltage was also measured. The degradation of VT is attributed to the oxide trap charges Qot. The extracted activation energy of 0.2 eV is related to a degradation dominated by the release of atomic hydrogen in La2O3 thin films.
Electrochemical and Solid State Letters | 2010
Po-Chin Chan; Ingram Yin-Ku Chang; Pi-Chun Juan; Joseph Ya-min Lee
In this work, Al/PbZr 0.53 Ti 0.47 O 3 /n + -polycrystalline silicon/Y 2 O 3 /Si capacitors and field-effect transistors were fabricated. The n + -polycrystalline silicon floating gate was used to reduce the depolarization field of the ferroelectric layer. The gate leakage was reduced (1.68 × 10 -10 A/cm 2 at 5 V) due to the large electron barrier height at the Y 2 O 3 /Si interface. The ratio (A c /A f ) of the control gate area A c and the floating gate area A f was varied from 1 to 0.25. An I DS -V GS memory window of 2.97 V was obtained at a sweeping voltage of 9 V with an A c /A f ratio of 0.25. An A c /A f area ratio less than 1 was preferred.