Pierre Mayr

A 22.3dB Voltage Gain 6.1dB NF 60GHz LNA in 65nm CMOS with Differential Output

This paper describes a 60GHz LNA, implemented in a 65nm digital CMOS technology, that has a single-ended input and a differenntial output. At 59.3GHz, the LNA achieves a maximum voltage gain of 22.3dB (power gain of 19.3dB). The input matching is better than -lOdB over the entire 3dB bandwidth from 55.8GHz to 63.5GHz. The LNA has a minimum measured NF of 6.1dB, an output compression point of +2.7dBm and draws 29mA from a 1.2V supply.

A 90GHz 65nm CMOS Injection-Locked Frequency Divider

Two injection-locked 2:1 frequency dividers for automotive radar applications achieve locking ranges from 82 to 94.1 GHz and from 34.3 to 42.1 GHz and consume 4mW and 8.4mW, respectively. The cascade of the two dividers can be locked from 79.7 to 81.6GHz. The 1mm2 chip is implemented in a 65nm CMOS process.

Improved RF-performance of sub-micron CMOS transistors by asymmetrically fingered device layout

This paper presents novel MOS-transistor layouts for analog RF applications. Asymmetrical drain and source diffusion areas as well as their contacting metal stacks are adjusted to improve the transistor performance. These modifications allow for increased device currents and reduced parasitic wiring capacitances simultaneously. Ring oscillators with transistors of identical channel width and length fabricated in a 65 nm digital CMOS technology are used for verification. An increase of 14% in oscillation frequency compared to classical multi-finger layouts corroborates the improvement by these modifications.

13 GHz cascaded 4:1 CMOS injection locked frequency divider

In this paper the first 4:1 injection locked frequency divider (ILFD) consisting of two cascaded divide-by-two LC-resonance ILFDs is presented. The locking range of the divider can be enhanced by optimal locking transistor biasing. For an input frequency of 13 GHz two ILFDs in standard 130 nm CMOS technology generate IQ-output signals within a locking range of 2.2 GHz without any varactor. The power consumption is 12 mW from a supply voltage of 1.5 V.

A 200 μm by 100 μm Smart Dust system with an average current consumption of 1.3 nA

In this paper we present a microscale “Smart Dust” type system with a volume of 200 μm × 100 μm × 10 μm, called lablet. The lablet contains a 20 Hz low power clock generator, a sensor, electric actuators and a simple finite state machine to implement a predefined response to the sensor input. The system operates with supply voltages ranging from 0.3 V to 1.8 V and is thus suitable to be supplied from a capacitor with decreasing voltage. An input rectifier allows powering the lablet independent of polarity. The average current consumption of the system was measured to be 1.3 nA when supplied from a capacitor with an initial voltage of 1.8 V. The system is intended to be used within electrolyte solutions. The small system scale allows the investigation of “pourable electronics”, a concept where large quantities of microsystems are deployed within a chemical solution to perform a predefined task. Several lablets have been designed and fabricated in a standard 180 nm CMOS process and the electrical functionality has been verified by contacting the lablet electrodes with multiple probe needles.